LPC2210/2220
NXP Semiconductors
6.20.2 PLL
16/32-bit ARM microcontrollers
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up into the range of 10 MHz to 60 MHz (LPC2210) and 10 MHz to
75 MHz (LPC2210/01 and LPC2220) with a Current Controlled Oscillator (CCO). The
multiplier can be an integer value from 1 to 32 (in practice, the multiplier value cannot be
higher than 6 on this family of microcontrollers due to the upper frequency limit of the
CPU). The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional
divider in the loop to keep the CCO within its frequency range while the PLL is providing
the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to
produce the output clock. Since the minimum output divider value is 2, it is insured that the
PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip
reset and may be enabled by software. The program must configure and activate the PLL,
wait for the PLL to Lock, then connect to the PLL as a clock source. The PLL settling time
is 100 µs.
6.20.3 Reset and wake-up timer
Reset has two sources on the LPC2210/2220: the RESET pin and watchdog reset. The
RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip
reset by any source starts the wake-up timer (see wake-up timer description below),
causing the internal chip reset to remain asserted until the external reset is de-asserted,
the oscillator is running, a fixed number of clocks have passed, and the on-chip circuitry
has completed its initialization.
When the internal reset is removed, the processor begins executing at address 0, which is
the reset vector. At that point, all of the processor and peripheral registers have been
initialized to predetermined values.
The wake-up timer ensures that the oscillator and other analog functions required for chip
operation are fully functional before the processor is allowed to execute instructions. This
is important at power-on, all types of reset, and whenever any of the aforementioned
functions are turned off for any reason. Since the oscillator and other functions are turned
off during Power-down mode, any wake-up of the processor from Power-down mode
makes use of the wake-up timer.
The wake-up timer monitors the crystal oscillator as the means of checking whether it is
safe to begin code execution. When power is applied to the chip, or some event caused
the chip to exit Power-down mode, some time is required for the oscillator to produce a
signal of sufficient amplitude to drive the clock logic. The amount of time depends on
many factors, including the rate of VDD ramp (in the case of power on), the type of crystal
and its electrical characteristics (if a quartz crystal is used), as well as any other external
circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing
ambient conditions.
6.20.4 External interrupt inputs
The LPC2210/2220 include up to nine edge or level sensitive external interrupt inputs as
selectable pin functions. When the pins are combined, external events can be processed
as four independent interrupt signals. The external interrupt inputs can optionally be used
to wake up the processor from Power-down mode.
LPC2210_2220_6
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 11 December 2008
29 of 50
NXP [ NXP ]
