LPC2210/2220
NXP Semiconductors
16/32-bit ARM microcontrollers
• Optional conversion on transition on input pin or Timer Match signal.
6.11.2 ADC features available in LPC2210/01 and LPC2220 only
• Every analog input has a dedicated result register to reduce interrupt overhead.
• Every analog input can generate an interrupt once the conversion is completed.
• The ADC pads are 5 V tolerant when configured for digital I/O function(s).
6.12 UARTs
The LPC2210/2220 each contain two UARTs. One UART provides a full modem control
handshake interface, the other provides only transmit and receive data lines.
6.12.1 Features
• 16 B receive and transmit FIFOs.
• Register locations conform to 16C550 industry standard.
• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
• Built-in baud rate generator.
• Standard modem interface signals included on UART1.
6.12.2 UART features available in LPC2210/01 and LPC2220 only
Compared to previous LPC2000 microcontrollers, UARTs in LPC2210/01 and LPC2220
introduce a fractional baud rate generator for both UARTs, enabling these microcontrollers
to achieve standard baud rates such as 115200 Bd with any crystal frequency above
2 MHz. In addition, auto-CTS/RTS flow-control functions are fully implemented in
hardware.
• Fractional baud rate generator enables standard baud rates such as 115200 Bd to be
achieved with any crystal frequency above 2 MHz.
• Auto-bauding.
• Auto-CTS/RTS flow-control fully implemented in hardware.
6.13 I2C-bus serial I/O controller
The I2C-bus is bidirectional for inter-IC control using only two wires: a serial clock line
(SCL), and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus, and it
can be controlled by more than one bus master connected to it.
The I2C-bus implemented in LPC2210/2220 supports a bit rate up to 400 kbit/s (fast
I2C-bus).
6.13.1 Features
• Compliant with standard I2C-bus interface.
• Easy to configure as master, slave, or master/slave.
LPC2210_2220_6
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 11 December 2008
24 of 50
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