NXP Semiconductors
FXPS7115D4
Digital absolute pressure sensor, 40 kPa to 115 kPa
Table 95.ꢀASICWFR_Y Register (address CDh) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Reset
Access
ASICWFR_Y[7:0]
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
Table 96.ꢀASICWLOT_L Register (address D0h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Reset
Access
ASICWLOT_L[7:0]
N/A N/A
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
R
R
Table 97.ꢀASICWLOT_H Register (address D1h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Reset
Access
ASICWLOT_H[7:0]
N/A N/A
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
R
R
7.7.30 USERDATA_0 to USERDATA_E - user data registers
User data registers are user programmable OTP registers that contain user-specific
information. These registers are included in the user programmed OTP array error
detection. These registers are readable and writable in SPI mode or I2C mode when
ENDINIT is not set.
7.7.31 USERDATA_10 to USERDATA_1E - user data registers
User data registers are user programmable OTP registers that contain user-specific
information. These registers are included in the user programmed OTP array error
detection. These registers are readable and writable in SPI mode or I2C mode when
ENDINIT is not set.
7.7.32 Lock and CRC Registers
The lock and CRC Registers are automatically programmed OTP registers that include
the lock bit, the block identifier, and the block OTP array CRC use for error detection.
These registers are automatically programmed when the corresponding data array is
programmed to OTP using the Write OTP Enable register.
FXPS7115D4
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© NXP B.V. 2019. All rights reserved.
Product data sheet
Rev. 3 — 5 December 2019
52 / 72
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