NXP Semiconductors
FXPS7115D4
Digital absolute pressure sensor, 40 kPa to 115 kPa
Table 89.ꢀSN1 Register (address C7h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Reset
Access
SN[7:0]
SN[7:0]
SN[7:0]
SN[7:0]
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
Table 90.ꢀSN2 Register (address C8h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Reset
Access
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
Table 91.ꢀSN3 Register (address C9h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Reset
Access
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
Table 92.ꢀSN4 Register (address CAh) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Reset
Access
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
7.7.29 ASIC wafer ID registers
The ASIC wafer ID registers are factory programmed OTP registers that include the
wafer number, wafer X and Y coordinates and the wafer lot number for the device ASIC.
These registers are included in the factory programmed OTP array error detection. These
registers are readable in SPI mode or I2C mode when ENDINIT is not set.
Table 93.ꢀASICWFR# Register (address CBh) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Reset
Access
ASICWFR#[7:0]
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
Table 94.ꢀASICWFR_X Register (address CCh) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Reset
Access
ASICWFR_X[7:0]
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
FXPS7115D4
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© NXP B.V. 2019. All rights reserved.
Product data sheet
Rev. 3 — 5 December 2019
51 / 72
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