NXP Semiconductors
FXPS7115D4
Digital absolute pressure sensor, 40 kPa to 115 kPa
Table 79.ꢀSNSDATA0_TIMEx - time stamp register (address 66h to 6Bh) bit allocation
Location
Address
66h
Bit
Symbol
7
6
5
4
3
2
1
0
SNSDATA0_TIME0
SNSDATA0_TIME1
SNSDATA0_TIME2
SNSDATA0_TIME3
SNSDATA0_TIME4
SNSDATA0_TIME5
SNSDATA0_TIME[7:0]
SNSDATA0_TIME[15:8]
SNSDATA0_TIME[23:16]
SNSDATA0_TIME[31:24]
SNSDATA0_TIME[39:32]
SNSDATA0_TIME[47:40]
67h
68h
69h
6Ah
6Bh
Factory default
Access
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
7.7.21 P_MAX, P_MIN - maximum and minimum absolute pressure value registers
(address 6Ch to 6Fh)
The minimum and maximum absolute pressure value registers are read-only registers
that contain a sample-by-sample continuously updated minimum and maximum 16-
bit absolute pressure value. The value is reset to 0000h on a write to a DSP_CFG_U1
register that changes the value of the LPF[2:0] or ST_CTRL[3:0].
These registers are readable in SPI mode or I2C mode. In I2C mode the P_xxx_H
register value is latched on a read of the P_xxx_L register value until the P_xxx_H
register is read. To avoid data mismatch, the user is required to always read the registers
in sequence, P_xxx_L register first, followed by the P_xxx_H register.
Table 80.ꢀP_Max and P_Min registers (address 6Ch to 6Fh) bit allocation
Location
Bit
Address
6Ch
Symbol
7
6
5
4
3
2
1
0
P_MAX_L
P_MAX_H
P_MIN_L
P_MIN_H
P_MAX[7:0]
6Dh
P_MAX[15:8]
P_MIN[7:0]
P_MIN[15:8]
6Eh
6Fh
Factory default
Access
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
7.7.22 FRT - free running timer registers (addresses 78h to 7Dh)
The free running timer registers are read-only registers that contain a 48-bit free running
timer. The free running timer is clocked by the main oscillator frequency and increments
every 100 ns.
Table 81.ꢀFRT - free running timer registers (addresses 78h to 7Dh) bit allocation
Location
Address
78h
Bit
Symbol
FRT0
FRT1
FRT2
FRT3
FRT4
FRT5
7
6
5
4
3
2
1
0
FRT[7:0]
FRT[15:8]
FRT[23:16]
FRT[31:24]
FRT[39:32]
FRT[47:40]
79h
7Ah
7Bh
7Ch
7Dh
Access
R
R
R
R
R
R
R
R
FXPS7115D4
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© NXP B.V. 2019. All rights reserved.
Product data sheet
Rev. 3 — 5 December 2019
48 / 72
NXP [ NXP ]
