NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
Effect
Bus
Opcode Operand Cycles
Address
on CCR
Source Form
Operation
Description
[1]
Mode
V H I N Z C
Transfer
Accumulator to
CCR
84
97
1
1
TAP
CCR ← (A)
Þ Þ Þ Þ Þ Þ INH
Transfer
Accumulator to X
(Index Register
Low)
TAX
TPA
X ← (A)
– – – – – – INH
– – – – – – INH
Transfer CCR to
Accumulator
85
1
A ← (CCR)
TST opr8a
TSTA
(M) – 0x00
(A) – 0x00
(X) – 0x00
(M) – 0x00
(M) – 0x00
(M) – 0x00
DIR
INH
3D dd
4D ꢁ
5D ꢁ
6D ff
4
1
1
4
3
5
TSTX
INH
0 – – Þ Þ –
IX1
Test for Negative
or Zero
TST oprx8,X
TST ,X
IX
7D ꢁ
9E6D ff
TST oprx8,SP
SP1
Transfer SP to
Index Reg.
H:X ← (SP) +
0x0001
95
2
TSX
TXA
– – – – – – INH
– – – – – – INH
– – – – – – INH
Transfer X (Index
Reg. Low) to
Accumulator
9F
1
A ← (X)
Transfer Index
Reg. to SP
SP ← (H:X) –
0x0001
94
8F
2
TXS
Enable Interrupts;
Wait for Interrupt
2+
WAIT
I bit ← 0; Halt CPU – – 0 – – – INH
[1] Bus clock frequency is one-half of the CPU clock frequency.
Table 76.ꢀOpcode map (Sheet 1 of 2)
Bit-Manipulation
Branch
Read-Modify-Write
Control
Register/Memory
00ꢁꢁ5 10ꢁꢁ5 20ꢁꢁ3 30ꢁꢁ5 40ꢁꢁ1 50ꢁꢁ1 60ꢁꢁ5 70ꢁꢁ4 80ꢁꢁ9 90ꢁꢁ3 A0ꢁꢁ2 B0ꢁꢁ3 C0ꢁꢁ4 D0ꢁꢁ4 E0ꢁꢁ3 F0ꢁꢁ3
BRSET0
BSET0
BRA
NEG
NEGA
NEGX
NEG
NEG
RTI
BGE
SUB
SUB
SUB
SUB
SUB
SUB
3ꢁꢁ
DIR
2ꢁꢁ
DIR
2ꢁꢁrel
2ꢁꢁ
DIR
1ꢁꢁ
INH
1ꢁꢁ
INH
2ꢁꢁIX1 1ꢁꢁIX
1ꢁꢁ
INH
2ꢁꢁrel
2ꢁꢁ
IMM
2ꢁꢁ
DIR
3ꢁꢁ
EXT
3ꢁꢁIX2 2ꢁꢁIX1 1ꢁꢁIX
01ꢁꢁ5 11ꢁꢁ5 21ꢁꢁ3 31ꢁꢁ5 41ꢁꢁ4 51ꢁꢁ4 61ꢁꢁ5 71ꢁꢁ5 81ꢁꢁ6 91ꢁꢁ3 A1ꢁꢁ2 B1ꢁꢁ3 C1ꢁꢁ4 D1ꢁꢁ4 E1ꢁꢁ3 F1ꢁꢁ3
BRCLR0
BCLR0
BRN
CBEQ
CBEQA
CBEQX
CBEQ
CBEQ
RTS
BLT
CMP
CMP
CMP
CMP
CMP
CMP
3ꢁꢁ
DIR
2ꢁꢁ
DIR
2ꢁꢁrel
3ꢁꢁ
DIR
3ꢁꢁ
IMM
3ꢁꢁ
IMM
3ꢁꢀIX1+ 2ꢁꢁIX+
1ꢁꢁ
INH
2ꢁꢁrel
2ꢁꢁ
IMM
2ꢁꢁ
DIR
3ꢁꢁ
EXT
3ꢁꢁIX2 2ꢁꢁIX1 1ꢁꢁIX
02ꢁꢁ5 12ꢁꢁ5 22ꢁꢁ3 32ꢁꢁ5 42ꢁꢁ5 52ꢁꢁ6 62ꢁꢁ1 72ꢁꢁ1 82ꢁꢁ5+ 92ꢁꢁ3 A2ꢁꢁ2 B2ꢁꢁ3 C2ꢁꢁ4 D2ꢁꢁ4 E2ꢁꢁ3 F2ꢁꢁ3
BRSET1
BSET1
BHI
LDHX
MUL
DIV
NSA
DAA
BGND
BGT
SBC
SBC
SBC
SBC
SBC
SBC
3ꢁꢁ
DIR
2ꢁꢁ
DIR
2ꢁꢁrel
3ꢁꢁ
EXT
1ꢁꢁ
INH
1ꢁꢁ
INH
1ꢁꢁ
INH
1ꢁꢁ
INH
1ꢁꢁ
INH
2ꢁꢁrel
2ꢁꢁ
IMM
2ꢁꢁ
DIR
3ꢁꢁ
EXT
3ꢁꢁIX2 2ꢁꢁIX1 1ꢁꢁIX
03ꢁꢁ5 13ꢁꢁ5 23ꢁꢁ3 33ꢁꢁ5 43ꢁꢁ1 53ꢁꢁ1 63ꢁꢁ5 73ꢁꢁ4 83ꢁꢁ11 93ꢁꢁ3 A3ꢁꢁ2 B3ꢁꢁ3 C3ꢁꢁ4 D3ꢁꢁ4 E3ꢁꢁ3 F3ꢁꢁ3
BRCLR1
BCLR1
BLS
COM
COMA
COMX
COM
COM
SWI
BLE
CPX
CPX
CPX
CPX
CPX
CPX
3ꢁꢁ
DIR
2ꢁꢁ
DIR
2ꢁꢁrel
2ꢁꢁ
DIR
1ꢁꢁ
INH
1ꢁꢁ
INH
2ꢁꢁIX1 1ꢁꢁIX
1ꢁꢁ
INH
2ꢁꢁrel
2ꢁꢁ
IMM
2ꢁꢁ
DIR
3ꢁꢁ
EXT
3ꢁꢁIX2 2ꢁꢁIX1 1ꢁꢁIX
04ꢁꢁ5 14ꢁꢁ5 24ꢁꢁ3 34ꢁꢁ5 44ꢁꢁ1 54ꢁꢁ1 64ꢁꢁ5 74ꢁꢁ4 84ꢁꢁ1 94ꢁꢁ2 A4ꢁꢁ2 B4ꢁꢁ3 C4ꢁꢁ4 D4ꢁꢁ4 E4ꢁꢁ3 F4ꢁꢁ3
BRSET2
BSET2
BCC
LSR
LSRA
LSRX
LSR
LSR
TAP
TXS
AND
AND
AND
AND
AND
AND
3ꢁꢁ
DIR
2ꢁꢁ
DIR
2ꢁꢁrel
2ꢁꢁ
DIR
1ꢁꢁ
INH
1ꢁꢁ
INH
2ꢁꢁIX1 1ꢁꢁIX
1ꢁꢁ
INH
1ꢁꢁ
INH
2ꢁꢁ
IMM
2ꢁꢁ
DIR
3ꢁꢁ
EXT
3ꢁꢁIX2 2ꢁꢁIX1 1ꢁꢁIX
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
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