NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
Tab. 84. Timer counter modulo register high
(TPM1MODH) (address $0013) ...................... 89
Tab. 85. Timer counter modulo register low
(TPM1MODL) (address $0014) .......................89
Tab. 86. Timer channel 0 status and control register
(TPM1C0SC) (address $0015) ........................89
Tab. 87. TPM1C0SC register field descriptions .............90
Tab. 88. Mode, edge, and level selection ......................90
Tab. 124. LFCTRLD register field descriptions ..............130
Tab. 125. LFR control register C (LFCTRLC, LPAGE =
1) (address $0023) ........................................131
Tab. 126. LFCTRLC register field descriptions ..............131
Tab. 127. LFR control register B (LFCTRLB, LPAGE =
1) (address $0024) ........................................132
Tab. 128. LFCTRLB register field descriptions ..............132
Tab. 129. LFR control register A (LFCTRLA, LPAGE =
1) (address $0025) ........................................132
Tab. 130. LFCTRLA register field descriptions ..............133
Tab. 131. Randomization interval times ........................ 139
Tab. 132. Frame number interval times ........................ 139
Tab. 133. RFM control register 0 (RFCR0) (address
$0030) ........................................................... 145
Tab. 89. Timer channel
(TPM1C0VH) (address $0016) ........................91
Tab. 90. Timer channel value register low
0
value register high
0
(TPM1C0VL) (address $0017) ........................ 91
Tab. 91. Timer channel 1 status and control register
(TPM1C1SC) (address $0018) ........................91
Tab. 92. TPM1C1SC register field descriptions .............92
Tab. 93. Mode, edge, and level selection ......................92
Tab. 134. RFCR0 field descriptions .............................. 145
Tab. 135. Data rate option examples ............................ 145
Tab. 136. RFM control register 1 (RFCR1) (address
$0031) ........................................................... 146
Tab. 137. RFCR1 field descriptions .............................. 146
Tab. 138. RFM control register 2 (RFCR2) (address
$0032) ........................................................... 146
Tab. 139. RFCR2 field descriptions .............................. 146
Tab. 140. RFM control register 3 (RFCR3) (address
$0033) ........................................................... 148
Tab. 141. RFCR3 field descriptions .............................. 148
Tab. 142. RFCR4 register — base time variable
(address $0034) ............................................ 149
Tab. 94. Timer channel
(TPM1C1VH) (address $0019) ........................93
Tab. 95. Timer channel value register low
1
value register high
1
(TPM1C1VL) (address $001A) ........................93
Tab. 96. ADC10 channel assignments ..........................99
Tab. 97. PWU divider register (PWUDIV) (address
$0038) ........................................................... 108
Tab. 98. PWUDIV register field descriptions ............... 108
Tab. 99. PWU Control/Status register 0 (PWUCS0)
(address $0039) ............................................ 109
Tab. 100. PWUSC0 register field descriptions .............. 109
Tab. 101. Limitations on clearing WUT/PRST ...............109
Tab. 102. PWU Control/Status register 1 (PWUCS1)
(address $003A) ............................................110
Tab. 143. RFCR4 field descriptions .............................. 149
Tab. 144. RFCR5 register — pseudo-random time
variable (address $0035) .............................. 149
Tab. 103. PWUSC1 register field descriptions .............. 110
Tab. 104. PWU wakeup status register (PWUS)
(address $001F) ............................................110
Tab. 145. RFCR5 field descriptions .............................. 150
Tab. 146. RFCR6 register — frame number time —
RFTS[1:0] = 1:0 (address $0036) ..................150
Tab. 105. PWUS register field descriptions ...................111
Tab. 106. LFR control register 1 (LFCTL1) (address
$0020) ........................................................... 122
Tab. 147. RFCR6 field descriptions .............................. 150
Tab. 148. RFM transmit control registers (RFCR7)
(address $0037) ............................................ 150
Tab. 107. LFCTL1 register field descriptions .................122
Tab. 108. LFR control register 2 (LFCTL2) (address
$0021) ........................................................... 123
Tab. 109. LFCTL2 register field descriptions .................123
Tab. 110. LFR control register 3 (LFCTL3) (address
($0022) .......................................................... 124
Tab. 149. RFCR7 field descriptions .............................. 151
Tab. 150. PLL control registers
RPAGE = 0) (address ($0038) ......................152
Tab. 151. PLL control registers (PLLCR[1:0],
A
(PLLCR[1:0],
A
RPAGE = 0) (address ($0039) ......................152
Tab. 152. PLLCR[1:0] field descriptions ........................152
Tab. 111. LFCTL3 register field descriptions .................125
Tab. 112. LFR control register 4 (LFCTL4) (address
$0023) ........................................................... 126
Tab. 153. PLL control registers
RPAGE = 0) (address $003A) .......................153
Tab. 154. PLL control registers (PLLCR[3:2],
B
(PLLCR[3:2],
B
Tab. 113. LFCTL4 register field descriptions .................126
Tab. 114. LFR status register (LFS, LPAGE = 0)
(address $0024) ............................................ 127
Tab. 115. LFS register field descriptions .......................127
Tab. 116. LFR data register (LFDATA) when LPAGE =
0 (address $0025) .........................................128
RPAGE = 0) (address $003B) .......................153
Tab. 155. PLLCR[3:2] field descriptions ........................153
Tab. 156. RFM EPR registers (EPR, RPAGE = 1,
VCD_EN = 0) (address $0038) ..................... 154
Tab. 157. RFM EPR registers (EPR, RPAGE = 1,
VCD_EN = 1) (address $0038) ..................... 154
Tab. 117. LFDATA register field descriptions ................129
Tab. 118. LFR ID low byte (LFIDL) (address $0026) .....129
Tab. 119. LFR ID high byte (LFIDH) (address $0027) ... 129
Tab. 120. LFR ID register field description ....................129
Tab. 121. LF control E (LFCTRLE) (address $0021) .....129
Tab. 122. LFCTRLE register field description ............... 130
Tab. 123. LFR control register D (LFCTRLD, LPAGE =
1) (address $0022) ........................................130
Tab. 158. EPR field descriptions ...................................154
Tab. 159. RF data registers (RFD[31:0]) .......................155
Tab. 160. RFD[31:0] field descriptions .......................... 155
Tab. 161. FXTH87Ex02 single Z-axis firmware
summary and jump routines ..........................157
Tab. 162. FXTH87Ex1x dual XZ-axis firmware
summary and jump routines ..........................159
Tab. 163. Device ID coding summary ........................... 160
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
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