NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
Tab. 164. Device ID coding descriptions .......................161
Tab. 165. BDC command summary .............................. 167
Tab. 166. BDC status and control register (BDCSCR) ...170
Tab. 167. BDCSCR register field descriptions ...............170
Tab. 168. System background debug force reset
register (SBDFR) ...........................................172
Tab. 169. SBDFR register field description ................... 172
Tab. 170. Revision history .............................................174
Figures
Fig. 1.
Fig. 2.
Fig. 3.
Fig. 4.
FXTH87E overall block diagram ....................... 4
Clock distribution ...............................................5
FXTH87E QFN package pinout ........................ 6
Fig. 28. Manchester encoded datagram for LFPOL =
0 .................................................................... 118
Fig. 29. Manchester encoded datagram for LFPOL =
1 .................................................................... 118
FXTH87E
QFN
optional
Z-axis
accelerometer orientation ..................................6
FXTH87E example application ..........................8
Recommended power supply connections ........9
RESET pin timing ............................................11
FXTH87E MCU memory map ......................... 17
FLASH program and erase flowchart ..............26
Fig. 30. Definition of duty-cycle of 40% ......................118
Fig. 31. Impact of duty-cycle on SYNC pattern .......... 119
Fig. 32. Antenna Q-factor equivalent model for the
LF envelope .................................................. 119
Fig. 5.
Fig. 6.
Fig. 7.
Fig. 8.
Fig. 9.
Fig. 33. LF envelope filtering ......................................119
Fig. 34. SYNC patterns .............................................. 120
Fig. 35. Telegram format (carrier preamble) ...............121
Fig. 36. LF detector sampling timing ..........................124
Fig. 37. RF transmitter block diagram ........................134
Fig. 38. Data frame formats ....................................... 136
Fig. 39. Datagram overview ....................................... 137
Fig. 40. Initial and interframe timing ...........................137
Fig. 41. LFSR implementation ....................................139
Fig. 42. Manchester data bit encoding (POL = 0) .......141
Fig. 43. Manchester data bit encoding (POL = 1) .......142
Fig. 44. Bi-Phase data bit encoding (POL = 0) ...........142
Fig. 45. Bi-Phase data bit encoding (POL = 1) ...........143
Fig. 46. RF power domains ........................................148
Fig. 47. VCO calibration state machine ......................156
Fig. 48. Measurement signal range definitions ...........162
Fig. 49. BDM tool connector ...................................... 164
Fig. 50. BDC host-to-target serial bit timing ............... 165
Fig. 51. BDC target-to-host serial bit timing (Logic 1) ..166
Fig. 52. BDM target-to-host serial bit timing (Logic 0) ..166
Fig. 10. FLASH burst program flowchart ......................27
Fig. 11. Block Protection Mechanism ...........................28
Fig. 12. Interrupt stack frame ....................................... 39
Fig. 13. General purpose I/O block diagram ................ 53
Fig. 14. General purpose I/O logic ...............................53
Fig. 15. KBI block diagram ...........................................59
Fig. 16. CPU registers ..................................................63
Fig. 17. Condition code register ................................... 65
Fig. 18. TPM1 block diagram ....................................... 86
Fig. 19. PWM period and pulse width (ELSnA = 0) ...... 96
Fig. 20. CPWM period and pulse width (ELSnA = 0) ....97
Fig. 21. Battery check circuit ......................................102
Fig. 22. Data flow for measurements ......................... 104
Fig. 23. Temperature restart response .......................105
Fig. 24. Flowchart for using TR module ..................... 106
Fig. 25. Wakeup timer block diagram .........................107
Fig. 26. Block diagram ............................................... 113
Fig. 27. FXTH87E LFR state machine diagram ..........116
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
179 / 183
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