Bus operations
NAND01G-B2B, NAND02G-B2C
Table 7.
Address insertion, x16 devices
I/O8-
Bus
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
cycle(1)
I/O15
1st
2nd
3rd
X
X
X
X
X
A7
VIL
A6
VIL
A5
VIL
A4
VIL
A3
VIL
A2
A10
A13
A21
VIL
A1
A9
A0
A8
A18
A26
VIL
A17
A25
VIL
A16
A24
VIL
A15
A23
VIL
A14
A22
VIL
A12
A20
VIL
A11
A19
A27
4th
5th(2)
1. Any additional address input cycles will be ignored.
2. The fifth cycle is valid for 2-Gbit devices. A27 is for 2-Gbit devices only.
Table 8.
Address definitions, x8
Address
Definition
A0 - A11
A12 - A17
A18 - A27
A18 - A28
Column address
Page address
Block address
Block address
1-Gbit device
2-Gbit device
Table 9.
Address definitions, x16
Address
Definition
A0 - A10
A11 - A16
A17 - A26
A17 - A27
Column address
Page address
Block address
Block address
1-Gbit device
2-Gbit device
18/60
NUMONYX [ NUMONYX B.V ]
