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M25PX64SOVME6TG 参数 Datasheet PDF下载

M25PX64SOVME6TG图片预览
型号: M25PX64SOVME6TG
PDF下载: 下载PDF文件 查看货源
内容描述: [EEPROM, 8MX8, Serial, CMOS, PDSO8, 8 X 6 MM, ROHS COMPLIANT, VDFPN-8]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
文件页数/大小: 68 页 / 1429 K
品牌: NUMONYX [ NUMONYX B.V ]
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M25PX64  
Instructions  
6.18  
Deep power-down (DP)  
Executing the deep power-down (DP) instruction is the only way to put the device in the  
lowest consumption mode (the deep power-down mode). It can also be used as a software  
protection mechanism, while the device is not in active use, as in this mode, the device  
ignores all write, program and erase instructions.  
Driving Chip Select (S) High deselects the device, and puts the device in the standby power  
mode (if there is no internal cycle currently in progress). But this mode is not the deep  
power-down mode. The deep power-down mode can only be entered by executing the deep  
power-down (DP) instruction, subsequently reducing the standby current (from ICC1 to ICC2  
,
as specified in Table 16).  
To take the device out of deep power-down mode, the release from deep power-down  
(RDP) instruction must be issued. No other instruction must be issued while the device is in  
deep power-down mode.  
The deep power-down mode automatically stops at power-down, and the device always  
powers up in the standby power mode.  
The deep power-down (DP) instruction is entered by driving Chip Select (S) Low, followed  
by the instruction code on serial data input (DQ0). Chip Select (S) must be driven Low for  
the entire duration of the sequence.  
The instruction sequence is shown in Figure 26.  
Chip Select (S) must be driven High after the eighth bit of the instruction code has been  
latched in, otherwise the deep power-down (DP) instruction is not executed. As soon as  
Chip Select (S) is driven High, it requires a delay of tDP before the supply current is reduced  
to ICC2 and the deep power-down mode is entered.  
Any deep power-down (DP) instruction, while an erase, program or write cycle is in  
progress, is rejected without having any effects on the cycle that is in progress.  
Figure 26. Deep power-down (DP) instruction sequence  
S
tDP  
0
1
2
3
4
5
6
7
C
Instruction  
DQ0  
Standby mode  
Deep power-down mode  
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