Numonyx™ StrataFlash® Cellular Memory (M18)
Upon power-up or exit from reset, the Read Configuration Register defaults to
asynchronous mode (RCR15 = 1; RCR[14:11] and RCR[9:0] are ignored).
To read the RCR value, issue the Read Device Information command to the desired
partition. Subsequent reads from the <partition base address> + 05h will output
RCR[15:0] on the data bus.
When using a Latency Count of Code 2 and a Data Hold of two cycles (CR9 = 1), WAIT
must be configured to deassert with valid data (CR8 = 0).
Table 31: Read Configuration Register Bit Definitions
Read Configuration Register (RCR)
Default: CR15 = 1
Burst Length
Read
WAIT
Polarity
WAIT
Delay
Latency Count
Mode
R
Reserved
15
14
13
12
11
10
9
8
7:3
2
1
0
Bit
Name
Description
0 = Synchronous burst-mode reads
15
Read Mode
1 = Asynchronous page-mode reads (default)
Bits: 14 13 12 11
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
=
=
=
=
=
=
=
=
=
=
3
4
5
6
7
8
9
14:11
Latency Count
10
11
12
(Other bit settings are reserved)
0
1
=
=
WAIT signal is active low (default)
WAIT signal is active high
10
WAIT Polarity
9
Reserved
WAIT Delay
Reserved
Write 0 to reserved bits
0
1
=
=
WAIT de-asserted with valid data
WAIT de-asserted one cycle before valid data (default)
8
7:3
Write 0 to reserved bits
0
0
1
1
1
1
0
1
1
=
=
=
8-word burst (wrap only)
16-word burst (wrap only)
Continuous-word burst (no-wrap; default) (Other bit settings
are reserved)
2:0
Burst Length
9.2.1
Latency Count
The Latency Count value programmed into RCR[14:11] is the number of valid CLK
edges from address-latch to the start of the data-output delay. When the Latency
Count has been satisfied, output data is driven after tCHQV.
Datasheet
78
April 2008
309823-10
NUMONYX [ NUMONYX B.V ]
