Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 46: Latency Count Period
Latency Count
CLK Latch (1)
CLK
ADV# (1)
ADV#-Latch (2)
ADV# (2)
A[Max:0]
CE#
OE#
tCHQV
DQ[15:0]
Notes:
1.
2.
Address latched on valid clock edge with ADV# low and LC count begins.
Address latched on ADV# rising edge. LC count begins on subsequent valid CLK edge.
Table 32: CLK Frequencies for LC Settings
VCCQ = 1.7 V to 2.0 V
Latency Count Setting
Frequency Supported (MHz)
3
≤ 32.6 MHz
≤ 43.5 MHz
≤ 54.3 MHz
≤ 65.2 MHz
≤ 76.1 MHz
≤ 87 MHz
4
5
6
7
8
9
≤ 97.8 MHz
≤ 108.7 MHz
≤ 119.6 MHz
≤ 130.4 MHz
≤ 133.3 MHz
10
11
12
13
9.3
Enhanced Configuration Register
The Enhanced Configuration Register (ECR) is a volatile 16-bit, read/write register used
to select Deep Power Down (DPD) operation and to modify the output-driver strength
of the flash device. All Enhanced Configuration Register bits are set and cleared using
the Program Enhanced Configuration Register command. Upon power-up or exit from
reset, the Enhanced Configuration Register defaults to 0004h.
To read the value of the ECR, issue the Read Device Information command to the
desired partition. Subsequent reads from the <partition base address> + 06h returns
ECR[15:0].
April 2008
309823-10
Datasheet
79
NUMONYX [ NUMONYX B.V ]
