Numonyx™ StrataFlash® Cellular Memory (M18)
While in DPD mode, the read-mode of each partition, configuration registers (RCR and
ECR), and block lock bits, are preserved. Status register is reset to 0080h; i.e., if the
Status register contains error bits, they will be cleared.
8.5
Standby
When CE# is deasserted, the device is deselected and placed in standby, substantially
reducing power consumption. In standby, data outputs are placed in high-Z,
independent of the level placed on OE#. If deselected during a Program or Erase
operation, the device continues to consume active power until the operation is
complete. There is no additional latency for subsequent read operations.
8.6
8.7
Output Disable
When OE# is deasserted with CE# asserted, the device outputs are disabled. Output
pins are placed in a high-impedance state. WAIT is deasserted in AD-muxed devices
and driven to High-Z in non-multiplexed devices.
Bus Cycle Interleaving
When issuing commands to the device, a read operation can occur between the two
write cycles of a 2-cycle command. (See Figure 43 and Figure 44) However, a write
operation cannot occur between the two write cycles of a 2-cycle command and will
cause a command sequence error (See Figure 45).
Figure 43: Operating Mode with Correct Command Sequence Example
Address [A]
WE# [W]
Partition A
Partition A
Partition B
OE# [G]
Data [D/Q]
0x20
0xD0
0xFF
Figure 44: Operating Mode with Correct Command Sequence Example
Address [A]
WE# [W]
Partition A
Partition B
Partition A
OE# [G]
Data [D/Q]
0x20
Valid Array Data
0xD0
Datasheet
74
April 2008
309823-10
NUMONYX [ NUMONYX B.V ]
