Numonyx™ StrataFlash® Cellular Memory (M18)
Figure 45: Operating Mode with Illegal Command Sequence Example
Address [A]
WE# [W]
Partition A
Partition B
Partition A
Partition A
OE# [G]
Data [D/Q]
0x20
0xFF
0xD0
SR[7:0]
8.7.1
Read Operation During Program Buffer fill
Due to the large buffer size of devices, the system interrupt latency may be impacted
during the buffer fill phase of a buffered programming operation. Please refer to the
relevant Application Note listed in Section 1.4, “Additional Information” on page 7 to
implement a software solution for your system.
8.8
Read-to-Write and Write-to-Read Bus Transitions
Consecutive read and write bus cycles must be properly separated from each other to
avoid bus contention. These cycle separation specs are described in the sections below.
8.8.1
8.8.2
Write to Asynchronous read transition
To transition from a bus write to an asynchronous read operation, either CE# or ADV#
must be toggled after WE# goes high.
Write to synchronous read transition
To transition from a bus write to a synchronous read operation, either CE# or ADV#
must be toggled after WE# goes high. In addition, W19 (tWHCH -WE# high to CLK high)
must be met.
8.8.3
8.8.4
Asynchronous/Synchronous read to write transition
To transition from a asynchronous/synchronous read to a write operation, either CE# or
ADV# must be toggled after OE# goes high.
Bus write with active clock
To perform a bus write when the device is in synchronous mode and the clock is active,
W21 (tVHWL- ADV# High to WE# Low) or W22 (tCHWL -Clock high to WE# low) must be
met.
April 2008
309823-10
Datasheet
75
NUMONYX [ NUMONYX B.V ]
