28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
1.2
Table 2.
Conventions
Conventions
Convention
Description
Used interchangeably to refer to the external signal connections on the
package.
Note:
Group Membership Brackets
Set
Clear:
Block
Main Block
Parameter Block
For a chip scale package (CSP), the term
ball
is used in place of
pin.
Pin or signal
Square brackets designate group membership or define a group of signals
with similar function (for example, A[21:1], SR[4:1])
When referring to registers, the term
set
means the bit is a logical 1.
When referring to registers, the term
clear
means the bit is a logical 0.
A group of bits (or words) that erase simultaneously using one block erase
instruction.
A block that contains 32 Kwords.
A block that contains 4 Kwords.
2.0
Functional Overview
The B3 flash memory device features the following:
•
Enhanced blocking for easy segmentation of code and data or additional design flexibility.
•
Program Suspend to Read command.
•
V
CCQ
input of 1.65 V to 2.5 V or 2.7 V to 3.6 V on all I/Os. See
through
for
pinout diagrams and V
CCQ
location.
•
Maximum program and erase time specification for improved data storage.
Table 3.
B3 Device Feature Summary (Sheet 1 of 2)
Feature
V
CC
Read Voltage
V
CCQ
I/O Voltage
V
PP
Program/Erase Voltage
Bus Width
Speed
8 bit
28F008B3, 28F016B3
2.7 V– 3.6 V
1.65 V–2.5 V or 2.7 V– 3.6 V
2.7 V– 3.6 V or 11.4 V– 12.6 V
16 bit
28F800B3, 28F160B3,
28F320B3
(3)
, 28F640B3
Reference
Section 4.2, 4.4
Section 4.2, 4.4
70 ns, 80 ns, 90 ns, 100 ns, 110 ns
512 Kbit x 16 (8 Mbit),
1024 Kbit x 16 (16 Mbit),
2048 Kbit x 16 (32 Mbit),
4096 Kbit x 16 (64 Mbit)
Memory Arrangement
1024 Kbit x 8 (8 Mbit),
2048 Kbit x 8 (16 Mbit)
18 Aug 2005
8
Intel
®
Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
Datasheet
NUMONYX [ NUMONYX B.V ]
