DS90C383A/DS90CF383A
Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
TCIT
TCIP
TCIH
TCIL
TxCLK IN Period
TxCLK IN High Time
TxCLK IN Low Time
Parameter
TxCLK IN Transition Time
14.7
0.35T
0.35T
T
0.5T
0.5T
Min
Typ
Max
5
55.6
0.65T
0.65T
Units
ns
ns
ns
ns
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
LLHT
LHLT
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TSTC
THTC
TCCD
TJCC
Parameter
LVDS Low-to-High Transition Time
LVDS High-to-Low Transition Time
Transmitter Output Pulse Position for Bit 0
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
Transmitter Output Pulse Position for Bit 0
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
Transmitter Output Pulse Position for Bit 0
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
TxIN Setup to TxCLK IN
TxIN Hold to TxCLK IN
TxCLK IN to TxCLK OUT Delay
T
A
=25˚C,V
CC
=3.3V
TxCLK IN to TxCLK OUT Delay
Transmitter Jitter Cycle-to-Cycle
(Figures 12, 13 )
f = 65 MHz
f = 40 MHz
f = 32.5 MHz
TPLLS
TPDD
Transmitter Phase Lock Loop Set
Transmitter Power Down Delay
f = 32.5 MHz
f = 40 MHz
f = 65 MHz
−0.30
1.90
4.10
6.30
8.50
10.70
12.90
−0.35
3.22
6.79
10.36
13.93
17.51
21.08
−0.40
4.00
8.40
12.80
17.20
21.60
26.00
2.5
0
3
3
175
240
260
5.5
7.0
225
380
400
10
100
Min
Typ
0.75
0.75
0
2.20
4.40
6.60
8.80
11.00
13.20
0
3.57
7.14
10.71
14.28
17.86
21.43
0
4.40
8.80
13.20
17.60
22.00
26.40
Max
1.5
1.5
0.20
2.40
4.60
6.80
9.00
11.20
13.40
0.35
3.92
7.49
11.06
14.63
18.21
21.78
0.40
4.80
9.20
13.60
18.00
22.40
26.80
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ms
ns
Note 5:
The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temperature ranges. This
parameter is functionality tested only on Automatic Test Equipment (ATE).
Note 6:
The Limits are based on statistical analysis of the device performance over process, voltage, and temperature ranges. Output jitter is measured with a
cycle-to-cycle jitter of 3ns applied to the input clock signal. A jitter event of 3ns, represents worse case jump in the clock edge from most Graphics controller VGA
chips currently available. This parameter is used when calculating system margin (RSKM). See Figures 12, 13 and AN-1059.
3
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