DS90C383A/DS90CF383A
DS90CF383A Pin Description—FPD Link Transmitter
Pin Name
TxIN
TxOUT+
TxOUT−
FPSHIFT IN
TxCLK OUT+
TxCLK OUT−
PWR DOWN
V
CC
GND
PLL V
CC
PLL GND
LVDS V
CC
LVDS GND
I/O
I
O
O
I
O
O
I
I
I
I
I
I
I
No.
28
4
4
1
1
1
1
4
4
1
2
1
3
Description
TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines — FPLINE,
FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).
Positive LVDS differential data output.
Negative LVDS differential data output.
TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN.
Positive LVDS differential clock output.
Negative LVDS differential clock output.
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power
down. See Applications Information section.
Power supply pins for TTL inputs.
Ground pins for TTL inputs.
Power supply pin for PLL.
Ground pins for PLL.
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
stopped, the PWR DOWN pin must be used to disable the
PLL. The PWR DOWN pin must be held low until after the
input clock signal has been reapplied. This will ensure a
proper device reset and PLL lock to occur.
POWER SEQUENCING AND POWERDOWN MODE
Outputs of the transmitter remain in TRI-STATE until the
power supply reaches 2V. Clock and data outputs will begin
to toggle 10 ms after V
CC
has reached 3V and the Power-
down pin is above 1.5V. Either device may be placed into a
powerdown mode at any time by asserting the Powerdown
pin (active low). Total power dissipation for each device will
decrease to 5 µW (typical).
The FPD Link chipset is designed to protect itself from
accidental loss of power to either the transmitter or receiver.
If power to the transmit board is lost, the receiver clocks
(input and output) stop. The data outputs (RxOUT) retain the
states they were in when the clocks stopped. When the
receiver board loses power, the receiver inputs are con-
trolled by a failsafe bias circuitry. The LVDS inputs are
High-Z during initial power on and power off conditions.
Current is limited (5 mA per input) by the fixed current mode
drivers, thus avoiding the potential for latchup when power-
ing the device.
RECEIVER FAILSAFE FEATURE
The FPD Link receivers have input failsafe bias circuitry to
guarantee a stable receiver output for floating or terminated
receiver inputs. Under these conditions receiver inputs will
be pulled to a HIGH state. This is the case if not all data
channels are required in the application. Leave the extra
channel’s inputs open. This minimizes power dissipation and
locks the unused channels outputs into a stable known
(HIGH) state.
If a clock signal is present, data outputs will all be HIGH; if
the clock input is also floating/terminated, data outputs will
remain in the last valid state. A floating/terminated clock
input will result in a LOW clock output.
Applications Information
The DS90C383A/DS90CF383A are backward compatible
with the DS90C383/DS90CF383 and are a pin-for-pin re-
placement. The device (DS90C383A/DS90CF383A) utilizes
a different PLL architecture employing an internal 7X clock
for enhanced pulse position control.
This device (DS90C383A/DS90CF383A) also features re-
duced variation of the TCCD parameter which is important
for dual pixel applications. (See AN-1084) TCCD variation
has been measured to be less than 250ps at 65MHz under
normal operating conditions.
This device may also be used as a replacement for the
DS90CF583 (5V, 65MHz) and DS90CF581 (5V, 40MHz)
FPD-Link Transmitters with certain considerations/
modifications:
1.
Change 5V power supply to 3.3V. Provide this supply to
the V
CC
, LVDS V
CC
and PLL V
CC
of the transmitter.
2. The DS90C383A transmitter input and control inputs
accept 3.3V TTL/CMOS levels. They are not 5V tolerant.
3.
To implement a falling edge device for the DS90C383A,
the R_FB pin (pin 17) may be tied to ground OR left
unconnected (an internal pull-down resistor biases this
pin low). Biasing this pin to Vcc implements a rising edge
device.
TRANSMITTER CLOCK JITTER CYCLE-TO-CYCLE
Figures 12 and 13 illustrate the timing of the input clock
relative to the input data. The input clock (TxCLKin) is inten-
tionally shifted to the left −3ns and +3ns to the right when
data (Txin0-27) is high. This 3ns of cycle-to-cycle clock jitter
is repeated at a period of 2µs, which is the period of the input
data (1µs high, 1µs low). At different operating frequencies
the N Cycle is changed to maintain the desired 3ns cycle-
to-cycle jitter at 2µs period.
TRANSMITTER INPUT CLOCK
The transmitter input clock must always be present when the
device is enabled (PWR DOWN = HIGH). If the clock is
9
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