DP83816
3.0 Functional Description
(Continued)
3.4 Physical Layer
The DP83816 has a full featured physical layer device with
integrated PMD sub-layers to support both 10BASE-T and
100BASE-TX Ethernet protocols. The physical layer is
designed for easy implementation of 10/100 Mb/s Ethernet
home or office solutions. It interfaces directly to twisted pair
media via an external transformer. The physical layer
utilizes on chip Digital Signal Processing (DSP) technology
and digital PLLs for robust performance under all operating
conditions, enhanced noise immunity, and lower external
component count when compared to analog solutions.
3.4.1 Auto-Negotiation
The Auto-Negotiation function provides a mechanism for
exchanging configuration information between two ends of
a link segment and automatically selecting the highest
performance mode of operation supported by both devices.
Fast Link Pulse (FLP) Bursts provide the signalling used to
communicate Auto-Negotiation abilities between two
devices at each end of a link segment. For further detail
regarding Auto-Negotiation, refer to Clause 28 of the IEEE
802.3u specification. The DP83816 supports four different
Ethernet protocols (10 Mb/s Half Duplex, 10 Mb/s Full
Duplex, 100 Mb/s Half Duplex, and 100 Mb/s Full Duplex),
so the inclusion of Auto-Negotiation ensures that the
highest performance protocol will be selected based on the
advertised ability of the Link Partner. The Auto-Negotiation
function within the DP83816 is controlled by internal
register access. Auto-Negotiation will be set at power-
up/reset, and also when a link status (up/valid) change
occurs.
3.4.2 Auto-Negotiation Register Control
When Auto-Negotiation is enabled, the DP83816 transmits
the abilities programmed into the Auto-Negotiation
Advertisement register (ANAR) via FLP Bursts. Any
combination of 10 Mb/s, 100 Mb/s, Half-Duplex, and Full
Duplex modes may be selected. The default setting of bits
[8:5] in the ANAR and bit 12 in the BMCR register are
determined at power-up.
The BMCR provides software with a mechanism to control
the operation of the DP83816. Bits 1 & 2 of the PHYSTS
register are only valid if Auto-Negotiation is disabled or
after Auto-Negotiation is complete. The Auto-Negotiation
protocol compares the contents of the ANLPAR and ANAR
registers and uses the results to automatically configure to
the highest performance protocol common to the local and
far-end port. The results of Auto-Negotiation may be
accessed in register C0h (PHYSTS), bit 4: Auto-
Negotiation Complete, bit 2: Duplex Status and bit 1:
Speed Status.
Auto-Negotiation Priority Resolution:
— (1) 100BASE-TX Full Duplex (Highest Priority)
— (2) 100BASE-TX Half Duplex
— (3) 10BASE-T Full Duplex
— (4) 10BASE-T Half Duplex (Lowest Priority)
The Basic Mode Control Register (BMCR) provides control
for enabling, disabling, and restarting the Auto-Negotiation
process. When Auto-Negotiation is disabled the Speed
Selection bit in the BMCR (bit 13) controls switching
between 10 Mb/s or 100 Mb/s operation, and the Duplex
Mode bit (bit 8) controls switching between full duplex
operation and half duplex operation. The Speed Selection
and Duplex Mode bits have no effect on the mode of
operation when the Auto-Negotiation Enable bit (bit 12) is
set.
The Basic Mode Status Register (BMSR) indicates the set
of available abilities for technology types, Auto-Negotiation
ability, and Extended Register Capability. These bits are
permanently set to indicate the full functionality of the
DP83816 (only the 100BASE-T4 bit is not set since the
DP83816 does not support that function).
The BMSR also provides status on:
— Auto-Negotiation complete (bit 5)
— Link Partner advertising that a remote fault has occurred
(bit 4)
— Valid link has been established (bit 2)
— Support for Management Frame Preamble suppression
(bit 6)
The Auto-Negotiation Advertisement Register (ANAR)
indicates the Auto-Negotiation abilities to be advertised by
the DP83816. All available abilities are transmitted by
default, but any ability can be suppressed by writing to the
ANAR. Updating the ANAR to suppress an ability is one
way for a management agent to change (force) the
technology that is used.
The Auto-Negotiation Link Partner Ability Register
(ANLPAR) is used to receive the base link code word as
well as all next page code words during the negotiation.
Furthermore, the ANLPAR will be updated to either 0081h
or 0021h for parallel detection to either 100 Mb/s or 10
Mb/s respectively.
The Auto-Negotiation Expansion Register (ANER)
indicates additional Auto-Negotiation status. The ANER
provides status on:
— Parallel Detect Fault occurrence (bit 4)
— Link Partner support of the Next Page function (bit 3)
— DP83816 support of the Next Page function (bit 2). The
DP83816 supports the Next Page function.
— Current page being exchanged by Auto-Negotiation has
been received (bit1)
— Link Partner support of Auto-Negotiation (bit 0)
3.4.3 Auto-Negotiation Parallel Detection
The DP83816 supports the Parallel Detection function as
defined in the IEEE 802.3u specification. Parallel Detection
requires both the 10 Mb/s and 100 Mb/s receivers to
monitor the receive signal and report link status to the
Auto-Negotiation function. Auto-Negotiation uses this
information to configure the correct technology in the event
that the Link Partner does not support Auto-Negotiation yet
is transmitting link signals that the 100BASE-TX or
10BASE-T PMAs (Physical Medium Attachments)
recognize as valid link signals.
If the DP83816 completes Auto-Negotiation as a result of
Parallel Detection, bits 5 and 7 within the ANLPAR register
will be updated to reflect the mode of operation present in
the Link Partner. Note that bits 4:0 of the ANLPAR will also
be set to 00001 based on a successful parallel detection to
indicate a valid 802.3 selector field. Software may
determine that negotiation completed via Parallel Detection
by reading the ANER (98h) register with bit 0, Link Partner
Auto-Negotiation Able bit, being reset to a zero, once the
Auto-Negotiation Complete bit, bit 5 of the BMSR (84h)
register is set to a one. If configured for parallel detect
16
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