DP83816
3.0 Functional Description
(Continued)
MAC INTERFACE
POWER ON
CONFIGURATION
PINS
TXD(3:0)
TXCLK
TXER
SERIAL
MANAGEMENT
RXD(3:0)
MDIO
MDC
COL
CRS
RXCLK
RXEN
RXER
RXDV
TXEN
RXCLK
TX_DATA
TX_DATA
TXCLK
REGISTERS
MII
PHY ADDRESS
NRZ TO
MANCHESTER
ENCODER
AUTO
NEGOTIATION
BASIC MODE
CONTROL
PCS CONTROL
LINK PULSE
GENERATOR
10BASE-T
100BASE-X
TRANSMIT
FILTER
FAR-END-FAULT
STATE MACHINE
RX_DATA
RXCLK
RECEIVE CHANNELS &
STATE MACHINES
100 MB/S
4B/5B
DECODER
CODE GROUP
ALIGNMENT
DESCRAMBLER
SERIAL TO
PARALLEL
NRZI TO NRZ
DECODER
CLOCK
RECOVERY
MLT-3 TO
BINARY
DECODER
ADAPTIVE
EQ
AND
BLW
COMP.
RECEIVE
FILTER
LINK PULSE
DETECTOR
10 MB/S
MANCHESTER
TO NRZ
DECODER
CLOCK
RECOVERY
TRANSMIT CHANNELS &
STATE MACHINES
100 MB/S
4B/5B
ENCODER
SCRAMBLER
PARALLEL TO
SERIAL
NRZ TO NRZI
ENCODER
BINARY TO
MLT-3
ENCODER
10 MB/S
10/100 COMMON
OUTPUT DRIVER
AUTO-NEGOTIATION
STATE MACHINE
SMART
SQUELCH
10/100 COMMON
INPUT BUFFER
CLOCK
GENERATION
LED
DRIVERS
TD
±
LEDS
RD
±
(ALSO FX_RD
±)
SYSTEM CLOCK
REFERENCE
Figure 3-4 DSP Physical Layer Block Diagram
15
NCLK_50M
RX_DATA
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