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DP83816AVNG 参数 Datasheet PDF下载

DP83816AVNG图片预览
型号: DP83816AVNG
PDF下载: 下载PDF文件 查看货源
内容描述: 10/100 Mb / s的集成PCI以太网媒体访问控制器和物理层( MacPHYTER - II ) [10/100 Mb/s Integrated PCI Ethernet Media Access Controller and Physical Layer (MacPHYTER-II )]
分类和应用: 控制器PC以太网局域网(LAN)标准
文件页数/大小: 106 页 / 815 K
品牌: NSC [ NATIONAL SEMICONDUCTOR ]
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DP83816
3.0 Functional Description
(Continued)
DP83816 conforms to 3.3V AC/DC specifications, but has
5V tolerant inputs.
PA
60b
SFD DA
4b
6B
SA
6B
LEN
2B
Data
46B-1500B
FCS
4B
3.3.2 Boot PROM
The BIOS ROM interface allows the DP83816 to read from
and write data to an external ROM/Flash device.
3.3.3 EEPROM
The DP83816 supports the attachment of an external
EEPROM. The EEPROM interface provides the ability for
the DP83816 to read from and write data to an external
serial EEPROM device. The DP83816 will auto-load values
from the EEPROM to certain fields in PCI configuration
Figure 3-3 Ethernet Packet Format
space and operational space and perform a checksum to
3.2.4 MIB
verify that the data is valid. Values in the external EEPROM
The MIB block contains counters to track certain media allow default fields in PCI configuration space and I/O
events required by the management specifications RFC space to be overridden following a hardware reset. If the
1213 (MIB II), RFC 1398 (Ether-like MIB), and IEEE 802.3 EEPROM is not present, the DP83816 initialization uses
LME. The counters provided are for events which are either default values for the appropriate Configuration and
difficult or impossible to be intercepted directly by software. Operational Registers. Software can read and write to the
Not all counters are implemented, however required EEPROM using “bit-bang” accesses via the EEPROM
Access Register (MEAR).
counters can be calculated from the counters provided.
3.3.4 Clock
3.3 Interface Definitions
Note: B = Bytes
b = bits
3.3.1 PCI System Bus
This interface allows direct connection of the DP83816 to a
33 MHz PCI system bus. The DP83816 supports zero wait
state data transfers with burst sizes up to 128 dwords. The
The clock interface provides the 25 MHz clock reference
input for the DP83816 IC. The X1 input signal amplitude
should be approximately 1V. This interface supports
operation from a 25 MHz, 50 ppm CMOS oscillator, or a 25
MHz, 50 ppm, parallel, 20 pF load, < 40
ESR crystal
resonator. A 20pF crystal resonator would require C1 and
14
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