DP83816
3.0 Functional Description
(Continued)
32
15
Data FIFO
32
Tx MAC
4
32
32
PCI Bus
32
PCI Bus
Interface
32
32
Data FIFO
Rx MAC
Rx Buffer Manager
4
32
MIB
32
Rx Filter
Pkt Recog
Logic
SRAM
16
MAC/BIU
93C46
Serial
EEPROM
Boot ROM/
Flash
Figure 3-2
MAC/BIU
Functional Block Diagram
3.1 MAC/BIU
The MAC/BIU is a derivative design from the DP83810
(Euphrates). The original MAC/BIU design has been
optimized to improve logic efficiency and enhanced to add
features consistent with current market needs and
specification compliance. The MAC/BIU design blocks are
discussed in this section.
control, serial EEPROM access with auto configuration
load, interrupt control, power management control with
support for PME or CLKRUN function.
3.1.1.1 Byte Ordering
The DP83816 can be configured to order the bytes of data
on the AD[31:0] bus to conform to little endian or big
3.1.1 PCI Bus Interface
endian ordering through the use of the Configuration
This block implements PCI v2.2 bus protocols, and Register, bit 0 (CFG:BEM). By default, the device is in little
configuration space. Supports bus master reads and writes endian ordering. Byte ordering only affects data FIFOs.
to CPU memory, and CPU access to on-chip register Register information remains bit aligned (i.e. AD[31] maps
space. Additional functions provided include: configuration to bit 31 in any register space, AD[0] maps to bit 0, etc.).
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Physical Layer Interface
Tx Buffer Manager
NSC [ NATIONAL SEMICONDUCTOR ]
