21.0 Memory Map
Address
Contents
All RAM, ports and registers (except A and PC) are mapped
into data memory address space.
S/ADD REG
xxBD
USART Baud Register (BAUD)
USART Prescale Select Register (PSR)
Reserved
xxBE
xxBF
xxC0
xxC1
xxC2
Address
Contents
S/ADD REG
Timer T2 Lower Byte
0000 to 006F On-Chip RAM bytes (112 bytes)
0070 to 007F Unused RAM Address Space (Reads As
All Ones)
Timer T2 Upper Byte
Timer T2 Autoload Register T2RA Lower
Byte
xx80 to xx90
Unused RAM Address Space (Reads As
Undefined Data)
xxC3
xxC4
xxC5
Timer T2 Autoload Register T2RA Upper
Byte
xx90 to xx9B
xx9C
Reserved
Timer T2 Autoload Register T2RB Lower
Byte
Programmable Gain Amplifier Offset
Trim Register for N Channel Pair
(AMPTRMN)
Timer T2 Autoload Register T2RB Upper
Byte
xx9D
Programmable Gain Amplifier Offset
Trim Register for P Channel Pair
(AMPTRMP)
xxC6
xxC7
Timer T2 Control Register
WATCHDOG Service Register
(Reg:WDSVR)
xx9E
xx9F
Reserved
Reserved
xxC8
MIWU Edge Select Register
(Reg:WKEDG)
xxA0 to xxA3 Reserved
xxC9
xxCA
xxCB
xxCC
MIWU Enable Register (Reg:WKEN)
MIWU Pending Register (Reg:WKPND)
A/D Converter Control Register (ENAD)
A/D Converter Result Register High Byte
(ADRSTH)
xxA4
xxA5
xxA6
xxA7
xxA8
Port B Data Register
Port B Configuration Register
Port B Input Pins (Read Only)
Reserved for Port B
ISP Address Register Low Byte
(ISPADLO)
xxCD
A/D Converter Result Register Low Byte
(ADRSTL)
xxA9
ISP Address Register High Byte
(ISPADHI)
xxCE
xxCF
xxD0
xxD1
xxD2
xxD3
xxD4
xxD5
xxD6
A/D Amplifier Gain Register (ADGAIN)
Idle Timer Control Register (ITMR)
Port L Data Register
xxAA
xxAB
ISP Read Data Register (ISPRD)
ISP Write Data Register (ISPWR)
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved
xxAC to xxAE Reserved
xxAF
High Speed Timers Control Register
(HSTCR)
xxB0
xxB1
xxB2
Timer T3 Lower Byte
Timer T3 Upper Byte
Timer T3 Autoload Register T3RA Lower
Byte
Port G Data Register
Port G Configuration Register
Port G Input Pins (Read Only)
xxD7 to xxDF Reserved
xxB3
xxB4
xxB5
Timer T3 Autoload Register T3RA Upper
Byte
xxE0
xxE1
Reserved
E2 and Flash Memory Write Timing
Register (PGMTIM)
Timer T3 Autoload Register T3RB Lower
Byte
xxE2
ISP Key Register (ISPKEY)
Timer T3 Autoload Register T3RB Upper
Byte
xxE3 to xxE5 Reserved
xxE6
Timer T1 Autoload Register T1RB Lower
xxB6
xxB7
xxB8
xxB9
xxBA
Timer T3 Control Register
Reserved
Byte
xxE7
Timer T1 Autoload Register T1RB Upper
Byte
USART Transmit Buffer (TBUF)
USART Receive Buffer (RBUF)
USART Control and Status Register
(ENU)
xxE8
xxE9
xxEA
xxEB
xxEC
ICNTRL Register
MICROWIRE/PLUS Shift Register
Timer T1 Lower Byte
Timer T1 Upper Byte
Timer T1 Autoload Register T1RA Lower
Byte
xxBB
xxBC
USART Receive Control and Status
Register (ENUR)
USART Interrupt and Clock Source
Register (ENUI)
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NSC [ National Semiconductor ]
