20.1.2 MICROWIRE/PLUS Slave Mode Operation
20.0 MICROWIRE/PLUS (Continued)
20.1 MICROWIRE/PLUS OPERATION
In the MICROWIRE/PLUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEL
bit in the CNTRL register enables the SO and SK functions
onto the G Port. The SK pin must be selected as an input
and the SO pin is selected as an output pin by setting and
resetting the appropriate bits in the Port G configuration
register. Table 38 summarizes the settings required to enter
the Slave mode of operation.
Setting the BUSY bit in the PSW register causes the
MICROWIRE/PLUS to start shifting the data. It gets reset
when eight data bits have been shifted. The user may reset
the BUSY bit by software to allow less than 8 bits to shift. If
enabled, an interrupt is generated when eight data bits have
been shifted. The device may enter the MICROWIRE/PLUS
mode either as a Master or as a Slave. Figure 34 shows how
two microcontroller devices and several peripherals may be
interconnected using the MICROWIRE/PLUS arrangements.
TABLE 38. MICROWIRE/PLUS Mode Settings
This table assumes that the control flag MSEL is set.
Warning:
G4 (SO)
G5 (SK)
G4
Fun.
SO
G5
The SIO register should only be loaded when the SK clock is
in the idle phase. Loading the SIO register while the SK clock
is in the active phase, will result in undefined data in the SIO
register.
Operation
Config. Bit Config. Bit
Fun.
1
0
1
0
1
1
0
0
Int. MICROWIRE/PLUS
SK Master
TRI-
STATE
SO
Int. MICROWIRE/PLUS
SK Master
Setting the BUSY flag when the input SK clock is in the
active phase while in the MICROWIRE/PLUS is in the slave
mode may cause the current SK clock for the SIO shift
register to be narrow. For safety, the BUSY flag should only
be set when the input SK clock is in the idle phase.
Ext. MICROWIRE/PLUS
SK Slave
TRI-
Ext. MICROWIRE/PLUS
SK Slave
STATE
20.1.1 MICROWIRE/PLUS Master Mode Operation
In the MICROWIRE/PLUS Master mode of operation the
shift clock (SK) is generated internally. The MICROWIRE/
PLUS Master always initiates all data exchanges. The MSEL
bit in the CNTRL register must be set to enable the SO and
SK functions onto the G Port. The SO and SK pins must also
be selected as outputs by setting appropriate bits in the Port
G configuration register. In the slave mode, the shift clock
stops after 8 clock pulses. Table 38 summarizes the bit
settings required for Master mode of operation.
The user must set the BUSY flag immediately upon entering
the Slave mode. This ensures that all data bits sent by the
Master is shifted properly. After eight clock pulses the BUSY
flag is clear, the shift clock is stopped, and the sequence
may be repeated.
20006335
FIGURE 34. MICROWIRE/PLUS Application
20.1.2.1 Alternate SK Phase Operation and SK Idle
Polarity
clock. The SIO register is shifted on each falling edge of the
SK clock. In the alternate SK phase operation, data is shifted
in on the falling edge of the SK clock and shifted out on the
rising edge of the SK clock. Bit 6 of Port G configuration
register selects the SK edge.
The device allows either the normal SK clock or an alternate
phase SK clock to shift data in and out of the SIO register. In
both the modes the SK idle polarity can be either high or low.
The polarity is selected by bit 5 of Port G data register. In the
normal mode data is shifted in on the rising edge of the SK
clock and the data is shifted out on the falling edge of the SK
A control flag, SKSEL, allows either the normal SK clock or
the alternate SK clock to be selected. Refer to Table 39 for
the appropriate setting of the SKSEL bit. The SKSEL is
65
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