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COP8AME9EMW8 参数 Datasheet PDF下载

COP8AME9EMW8图片预览
型号: COP8AME9EMW8
PDF下载: 下载PDF文件 查看货源
内容描述: 8位CMOS闪存微控制器,具有8K内存,双通道运算放大器,虚拟EEROM ,温度传感器, 10位A / D和掉电复位 [8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEROM, Temperature Sensor,10-Bit A/D and Brownout Reset]
分类和应用: 闪存传感器温度传感器微控制器和处理器外围集成电路运算放大器光电二极管时钟
文件页数/大小: 83 页 / 908 K
品牌: NSC [ National Semiconductor ]
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12.0 Timers (Continued)  
12.3 TIMER CONTROL FLAGS  
the external event occurs. The capture register eliminates  
the latency time, thereby allowing the applications program  
to retrieve the timer value stored in the capture register.  
The control bits and their functions are summarized below.  
TxC3  
TxC2  
TxC1  
TxC0  
Timer mode control  
Timer mode control  
Timer mode control  
In this mode, the timer Tx is constantly running at the fixed tC  
or MCLK rate. The two registers, RxA and RxB, act as  
capture registers. Each register also acts in conjunction with  
a pin. The register RxA acts in conjunction with the TxA pin  
and the register RxB acts in conjunction with the TxB pin.  
Timer Start/Stop control in Modes 1 and 2 (Pro-  
cessor Independent PWM and External Event  
Counter), where 1 = Start, 0 = Stop  
Timer Underflow Interrupt Pending Flag in Mode  
3 (Input Capture)  
The timer value gets copied over into the register when a  
trigger event occurs on its corresponding pin after synchro-  
nization to the appropriate internal clock (tC or MCLK). Con-  
trol bits, TxC3, TxC2 and TxC1, allow the trigger events to be  
specified either as a positive or a negative edge. The trigger  
condition for each input pin can be specified independently.  
TxPNDA Timer Interrupt Pending Flag  
TxENA Timer Interrupt Enable Flag  
1 = Timer Interrupt Enabled  
0 = Timer Interrupt Disabled  
The trigger conditions can also be programmed to generate  
interrupts. The occurrence of the specified trigger condition  
on the TxA and TxB pins will be respectively latched into the  
pending flags, TxPNDA and TxPNDB. The control flag  
TxENA allows the interrupt on TxA to be either enabled or  
disabled. Setting the TxENA flag enables interrupts to be  
generated when the selected trigger condition occurs on the  
TxA pin. Similarly, the flag TxENB controls the interrupts  
from the TxB pin.  
TxPNDB Timer Interrupt Pending Flag  
TxENB Timer Interrupt Enable Flag  
1 = Timer Interrupt Enabled  
0 = Timer Interrupt Disabled  
The timer mode control bits (TxC3, TxC2 and TxC1) are  
detailed in Table 15, Timer Operating Modes.  
When the high speed timers are counting in high speed  
mode, directly altering the contents of the timer upper or  
lower registers, the PWM outputs or the reload registers is  
not recommended. Bit operations can be particularly prob-  
lematic. Since any of these six registers or the PWM outputs  
can change as many as ten times in a single instruction  
cycle, performing an SBIT or RBIT operation with the timer  
running can produce unpredictable results. The recom-  
mended procedure is to stop the timer, perform any changes  
to the timer, the PWM outputs or reload register values, and  
then re-start the timer. This warning does not apply to the  
timer control register. Any type of read/write operation, in-  
cluding SBIT and RBIT may be performed on this register in  
any operating mode.  
Underflows from the timer can also be programmed to gen-  
erate interrupts. Underflows are latched into the timer TxC0  
pending flag (the TxC0 control bit serves as the timer under-  
flow interrupt pending flag in the Input Capture mode). Con-  
sequently, the TxC0 control bit should be reset when enter-  
ing the Input Capture mode. The timer underflow interrupt is  
enabled with the TxENA control flag. When a TxA interrupt  
occurs in the Input Capture mode, the user must check both  
the TxPNDA and TxC0 pending flags in order to determine  
whether a TxA input capture or a timer underflow (or both)  
caused the interrupt.  
Figure 17 shows a block diagram of the timer T1 in Input  
Capture mode. T2 and T3 are identical to T1.  
20006321  
FIGURE 17. Timer in Input Capture Mode  
33  
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