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30151-33 参数 Datasheet PDF下载

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型号: 30151-33
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内容描述: 的Geode ™ GXM处理器与MMX支持集成的x86解决方案 [Geode⑩ GXm Processor Integrated x86 Solution with MMX Support]
分类和应用:
文件页数/大小: 244 页 / 4221 K
品牌: NSC [ National Semiconductor ]
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Processor Programming (Continued)  
3.3.2 System Register Set  
Table 3-5. System Register Set  
The system register set, shown in Table 3-5, consists of  
registers not generally used by application programmers.  
These registers are typically employed by system level  
programmers who generate operating systems and mem-  
ory management programs. Associated with the system  
register set are certain tables and segments which are  
listed in Table 3-5.  
Width  
(Bits)  
Group  
Control  
Name  
CR0  
Function  
System Control  
Register  
32  
32  
32  
Registers  
CR2  
CR3  
Page Fault Linear  
Address Register  
Page Directory Base  
Register  
The Control Registers control certain aspects of the  
GXm processor such as paging, coprocessor functions,  
and segment protection.  
CR4  
GDT  
IDT  
Time Stamp Counter  
32  
32  
32  
Descriptor  
Tables  
General Descriptor Table  
The Descriptor Tables hold descriptors that manage  
memory segments and tables, interrupts and task switch-  
ing. The tables are defined by corresponding registers.  
Interrupt Descriptor  
Table  
LDT  
Local Descriptor Table  
GDT Register  
16  
32  
32  
16  
16  
The two Task State Segments Tables defined by TSS reg-  
ister are used to save and load the computer state when  
switching tasks.  
Descriptor  
Table  
Registers  
GDTR  
IDTR  
LDTR  
TSS  
IDT Register  
LDT Register  
The Configuration Registers are used to define the  
GXm CPU setup including cache management.  
Task State  
Segment and  
Registers  
Task State Segment  
Tables  
TR  
TSS Register Setup  
16  
8
The ID registers allow BIOS and other software to identify  
the specific CPU and stepping. System Management  
Mode (SMM) control information is stored in the SMM reg-  
isters.  
Configuration CCRn  
Registers  
Configuration Control  
Registers  
ID  
DIRn  
Device Identification  
Registers  
8
8
Registers  
The Debug Registers provide debugging facilities for the  
GXm processor and enable the use of data access break-  
points and code execution breakpoints.  
SMM  
Registers  
SMARn  
SMHRn  
SMM Address Region  
Registers  
SMM Header Addresses  
8
8
The Test Registers provide a mechanism to test the con-  
tents of both the on-chip 16 KB cache and the Translation  
Lookaside Buffer (TLB). The TLB is used as a cache for  
the tables that are used in to translate linear addresses to  
physical addresses while paging is enabled.  
Performance PCR0  
Registers  
Performance Control  
Register  
Debug  
Registers  
DR0  
DR1  
DR2  
DR3  
Linear Breakpoint  
Address 0  
32  
32  
32  
32  
Linear Breakpoint  
Address 1  
Table 3-5 lists the system register sets along with their  
size and function.  
Linear Breakpoint  
Address 2  
Linear Breakpoint  
Address 3  
DR6  
DR7  
TR3  
TR4  
TR5  
TR6  
TR7  
Breakpoint Status  
Breakpoint Control  
Cache Test  
32  
32  
32  
32  
32  
32  
32  
Test  
Registers  
Cache Test  
Cache Test  
TLB Test Control  
TLB Test Status  
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