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30151-33 参数 Datasheet PDF下载

30151-33图片预览
型号: 30151-33
PDF下载: 下载PDF文件 查看货源
内容描述: 的Geode ™ GXM处理器与MMX支持集成的x86解决方案 [Geode⑩ GXm Processor Integrated x86 Solution with MMX Support]
分类和应用:
文件页数/大小: 244 页 / 4221 K
品牌: NSC [ National Semiconductor ]
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Processor Programming (Continued)  
3.3.2.1 Control Registers  
the general state of the CPU. The lower 16 bits of CR0 are  
referred to as the Machine Status Word (MSW).  
A map of the Control Registers (CR0, CR2, CR3, and  
CR4) is shown in Table 3-6 and the bit definitions are given  
in Table 3-7. (These registers should not be confused with  
the CRRn registers.) The CR0 register contains system  
control bits which configure operating modes and indicate  
When operating in real mode, any program can read and  
write the control registers. In protected mode, however,  
only privilege level 0 (most-privileged) programs can read  
and write these registers.  
Table 3-6. Control Registers Map  
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  
9
8
7
6
5
4
3
2
1
0
CR4 Register  
Control Register 4 (R/W)  
RSVD  
T
S
C
RSVD  
CR3 Register  
CR2 Register  
CR1 Register  
CR0 Register  
Control Register 3 (R/W)  
PDBR (Page Directory Base Register)  
RSVD  
0
0
RSVD  
Control Register 2 (R/W)  
PFLA (Page Fault Linear Address)  
Control Register 1 (R/W)  
RSVD  
Control Register 0 (R/W)  
P
G
C
D
N
W
RSVD  
A
M
R
S
V
D
W
P
RSVD  
N
E
R
S
V
D
T
S
E
M
M
P
P
E
Machine Status Word (MSW)  
Table 3-7. CR4-CR0 Bit Definitions  
Bit  
Name Description  
CR4 Register  
Control Register 4 (R/W)  
31:3  
2
RSVD Reserved: Set to 0 (always returns 0 when read).  
TSC  
Time Stamp Counter Instruction:  
If = 1 RDTSC instruction enabled for CPL = 0 only; reset state.  
If = 0 RDTSC instruction enabled for all CPL states.  
1:0  
RSVD Reserved: Set to 0 (always returns 0 when read).  
Control Register 3 (R/W)  
CR3 Register  
31:12  
11:0  
PDBR Page Directory Base Register: Identifies page directory base address on a 4 KB page boundary.  
RSVD Reserved: Set to 0.  
CR2 Register  
Control Register 2 (R/W)  
31:0  
PFLA  
Page Fault Linear Address: With paging enabled and after a page fault, PFLA contains the linear address of the  
address that caused the page fault.  
CR1 Register  
Control Register 1 (R/W)  
31:0  
RSVD Reserved  
CR0 Register  
Control Register 0 (R/W)  
31  
PG  
Paging Enable Bit: If PG = 1 and protected mode is enabled (PE = 1), paging is enabled. After changing the  
state of PG, software must execute an unconditional branch instruction (e.g., JMP, CALL) to have the change  
take effect.  
Revision 3.1  
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