欢迎访问ic37.com |
会员登录 免费注册
发布采购

30151-33 参数 Datasheet PDF下载

30151-33图片预览
型号: 30151-33
PDF下载: 下载PDF文件 查看货源
内容描述: 的Geode ™ GXM处理器与MMX支持集成的x86解决方案 [Geode⑩ GXm Processor Integrated x86 Solution with MMX Support]
分类和应用:
文件页数/大小: 244 页 / 4221 K
品牌: NSC [ National Semiconductor ]
 浏览型号30151-33的Datasheet PDF文件第43页浏览型号30151-33的Datasheet PDF文件第44页浏览型号30151-33的Datasheet PDF文件第45页浏览型号30151-33的Datasheet PDF文件第46页浏览型号30151-33的Datasheet PDF文件第48页浏览型号30151-33的Datasheet PDF文件第49页浏览型号30151-33的Datasheet PDF文件第50页浏览型号30151-33的Datasheet PDF文件第51页  
Processor Programming (Continued)  
3.3.2.2 Configuration Registers  
Each data transfer through I/O Port 23h must be preceded  
by a register index selection through I/O Port 22h; other-  
wise, subsequent I/O Port 23h operations are directed off-  
chip and produce external I/O cycles.  
The configuration registers listed in Table 3-9 are CPU  
registers and are selected by register index numbers. The  
registers are accessed through I/O memory locations 22h  
and 23h. Registers are selected for access by writing an  
index number to I/O Port 22h using an OUT instruction  
prior to transferring data through I/O Port 23h.  
If MAPEN, bit 4 of CCR3 (Index C3h[4]) = 0, external I/O  
cycles occur if the register index number is outside the  
range C0h-CFh, FEh, and FFh. The MAPEN bit should  
remain 0 during normal operation to allow system regis-  
ters located at I/O Port 22h to be accessed.  
Table 3-9. Configuration Register Summary  
Access Default  
Reference  
Index  
Type  
Name  
Controlled By*  
Value  
(Bit Formats)  
C1h  
C2h  
C3h  
E8h  
EBh  
20h  
B0h  
B1h  
B2h  
B3h  
B8h  
B9h  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
CCR1 — Configuration Control 1  
CCR2 — Configuration Control 2  
CCR3 — Configuration Control 3  
CCR4 — Configuration Control 4  
CCR7 — Configuration Control 7  
PCR — Performance Control  
SMI_LOCK  
--  
00h  
00h  
00h  
85h  
00h  
07h  
xxh  
xxh  
xxh  
xxh  
00h  
00h  
00h  
Table 3-11 on page 49  
Table 3-11 on page 49  
Table 3-11 on page 49  
Table 3-11 on page 50  
Table 3-11 on page 50  
Table 3-11 on page 50  
Table 3-11 on page 50  
Table 3-11 on page 50  
Table 3-11 on page 50  
Table 3-11 on page 50  
Table 4-1 on page 92  
Table 5-5 on page 173  
Table 5-5 on page 173  
SMI_LOCK  
MAPEN  
--  
MAPEN  
MAPEN  
MAPEN  
MAPEN  
MAPEN  
MAPEN  
--  
SMHR0 — SMM Header Address 0  
SMHR1 — SMM Header Address 1  
SMHR2 — SMM Header Address 2  
SMHR3 — SMM Header Address 3  
GCR — Graphics Control Register  
VGACTL — VGA Control Register  
VGAM0 — VGA Mask Register  
BAh-  
BDh  
--  
CDh  
CEh  
CFh  
FEh  
FFh  
R/W  
R/W  
R/W  
RO  
SMAR0 — SMM Address 0  
SMAR1 — SMM Address 1  
SMAR2 — SMM Address 2  
DIR0 — Device ID 0  
SMI_LOCK  
00h  
00h  
00h  
4xh  
xxh  
Table 3-11 on page 51  
Table 3-11 on page 51  
Table 3-11 on page 51  
Table 3-11 on page 51  
Table 3-11 on page 51  
SMI_LOCK  
SMI_LOCK  
--  
--  
RO  
DIR1 — Device ID 1  
Note: *MAPEN = Index C3h[4] (CCR3) and SMI_LOCK = Index C3h[0] (CCR3).  
Revision 3.1  
47  
www.national.com  
 复制成功!