Processor Programming (Continued)
3.3 REGISTER SETS
The accessible registers in the processor are grouped into
three sets:
3.3.1.1 General Purpose Registers
The General Purpose Registers are divided into four data
registers, two pointer registers, and two index registers as
shown in Table 3-2.
1) The Application Register Set contains the registers
frequently used by application programmers. Table 3-
2 shows the general purpose, segment, the instruc-
tion pointer and the EFLAGS Registers.
The Data Registers are used by the applications pro-
grammer to manipulate data structures and to hold the
results of logical and arithmetic operations. Different por-
tions of general data registers can be addressed by using
different names.
2) The System Register Set contains the registers typi-
cally reserved for operating-systems programmers:
control, system address, debug, configuration, and
test registers.
An “E” prefix identifies the complete 32-bit register. An “X”
suffix without the “E” prefix identifies the lower 16 bits of
the register.
3) The Model Specific Register (MSR) Set is used to
monitor the performance of the processor or a
specific component within the processor. The model
specific register set has one 64-bit register called the
Time Stamp Counter.
The lower two bytes of a data register are addressed with
an “H” suffix (identifies the upper byte) or an “L” suffix (iden-
tifies the lower byte). These _L and _H portions of the
data registers act as independent registers. For example,
if the AH register is written to by an instruction, the AL reg-
ister bits remain unchanged.
Each of these register sets are discussed in detail in the
subsections that follow. Additional registers to support
integrated GXm processor subsystems are described in
Section 4.1 “Integrated Functions Programming Interface”
on page 92.
The Pointer and Index Registers are listed below.
SI or ESI
Source Index
Destination Index
Stack Pointer
Base Pointer
3.3.1 Application Register Set
DI or EDI
SP or ESP
BP or EBP
The Application Register Set consists of the registers most
often used by the applications programmer. These regis-
ters are generally accessible, although some bits in the
EFLAGS register are protected.
These registers can be addressed as 16- or 32-bit registers,
with the “E” prefix indicating 32 bits. The pointer and index
registers can be used as general purpose registers; how-
ever, some instructions use a fixed assignment of these
registers. For example, repeated string operations always
use ESI as the source pointer, EDI as the destination
pointer, and ECX as a counter. The instructions that use
fixed registers include multiply and divide, I/O access,
string operations, stack operations, loop, variable shift and
rotate, and translate instructions.
The General Purpose Register contents are frequently
modified by instructions and typically contain arithmetic
and logical instruction operands.
In real mode, Segment Registers contain the base
address for each segment. In protected mode, the seg-
ment registers contain segment selectors. The segment
selectors provide indexing for tables (located in memory)
that contain the base address for each segment, as well
as other memory addressing information.
The GXm processor implements a stack using the ESP
register. This stack is accessed during the PUSH and
POP instructions, procedure calls, procedure returns,
interrupts, exceptions, and interrupt/exception returns.
The GXm processor automatically adjusts the value of the
ESP during operations that result from these instructions.
The Instruction Pointer Register points to the next
instruction that the processor will execute. This register is
automatically incremented by the processor as execution
progresses.
The EFLAGS Register contains control bits used to
reflect the status of previously executed instructions. This
register also contains control bits that affect the operation
of some instructions.
The EBP register may be used to refer to data passed on
the stack during procedure calls. Local data may also be
placed on the stack and accessed with BP. This register
provides a mechanism to access tack data in high-level
languages.
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