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30151-33 参数 Datasheet PDF下载

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型号: 30151-33
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内容描述: 的Geode ™ GXM处理器与MMX支持集成的x86解决方案 [Geode⑩ GXm Processor Integrated x86 Solution with MMX Support]
分类和应用:
文件页数/大小: 244 页 / 4221 K
品牌: NSC [ National Semiconductor ]
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3.0 Processor Programming  
This section describes the internal operations of the  
Geode GXm processor from a programmer’s point of view.  
It includes a description of the traditional “core” process-  
ing and FPU operations. The integrated function registers  
are described at the end of this chapter.  
3.1 CORE PROCESSOR INITIALIZATION  
The GXm processor is initialized when the RESET signal  
is asserted. The processor is placed in real mode and the  
registers listed in Table 3-1 are set to their initialized val-  
ues. RESET invalidates and disables the CPU cache, and  
turns off paging. When RESET is asserted, the CPU ter-  
minates all local bus activity and all internal execution.  
During the entire time that RESET is asserted, the inter-  
nal pipeline is flushed and no instruction execution or bus  
activity occurs.  
The primary register sets within the processor core  
include:  
Application Register Set  
System Register Set  
Model Specific Register Set  
Floating Point Unit Register Set.  
Approximately 150 to 250 external clock cycles after  
RESET is deasserted, the processor begins executing  
instructions at the top of physical memory (address loca-  
tion FFFFFFF0h). The actual time depends on the clock  
scaling in use. Also, an additional 220 clock cycles are  
needed when self-test is requested.  
The initialization of the major registers within in core are  
shown in Table 3-1.  
The integrated function sets are located in main memory  
space and include:  
Typically, an intersegment jump is placed at FFFFFFF0h.  
This instruction will force the processor to begin execution  
in the lowest 1 MB of address space.  
Internal Bus Interface Unit Register Set  
Graphics Pipeline Register Set  
Display Controller Register Set  
Memory Controller Register Set  
Power Management Register Set  
The following table, Table 3-1, lists the core registers and  
illustrates how they are initialized.  
Table 3-1. Initialized Core Register Controls  
Register  
Register Name  
Accumulator  
Initialized Contents  
Comments  
EAX  
EBX  
ECX  
EDX  
EBP  
ESI  
xxxxxxxxh  
xxxxxxxxh  
xxxxxxxxh  
xxxx 04 [DIR0]h  
xxxxxxxxh  
xxxxxxxxh  
xxxxxxxxh  
xxxxxxxxh  
00000002h  
0000FFF0h  
0000h  
00000000h indicates self-test passed.  
Base  
Count  
Data  
DIR0 = Device ID  
Base Pointer  
Source Index  
Destination Index  
Stack Pointer  
Extended FLAGS  
Instruction Pointer  
Extra Segment  
Code Segment  
Stack Segment  
Data Segment  
Extra Segment  
Extra Segment  
EDI  
ESP  
EFLAGS  
EIP  
See Table 3-4 on page 43 for bit definitions.  
ES  
Base address set to 00000000h. Limit set to FFFFh.  
Base address set to FFFF0000h. Limit set to FFFFh.  
Base address set to 00000000h. Limit set to FFFFh.  
Base address set to 00000000h. Limit set to FFFFh.  
Base address set to 00000000h. Limit set to FFFFh.  
Base address set to 00000000h. Limit set to FFFFh.  
CS  
F000h  
SS  
0000h  
DS  
0000h  
FS  
0000h  
GS  
0000h  
IDTR  
GDTR  
LDTR  
TR  
Interrupt Descriptor Table Register Base = 0, Limit = 3FFh  
Global Descriptor Table Register  
Local Descriptor Table Register  
Task Register  
xxxx xxxxh  
xxxxh  
xxxxh  
CR0  
CR2  
CR3  
CR4  
CCR1  
CCR2  
CCR3  
CCR7  
SMAR0  
Machine Status Word  
Control Register 2  
60000010h  
xxxxxxxxh  
xxxxxxxxh  
00000000h  
00h  
See Table 3-7 on page 49 for bit definitions.  
See Table 3-7 on page 49 for bit definitions.  
See Table 3-7 on page 49 for bit definitions.  
See Table 3-7 on page 49 for bit definitions.  
See Table 3-11 on page 49 for bit definitions.  
See Table 3-11 on page 49 for bit definitions.  
See Table 3-11 on page 49 for bit definitions.  
See Table 3-11 on page 50 for bit definitions.  
See Table 3-11 on page 51 for bit definitions.  
Control Register 3  
Control Register 4  
Configuration Control 1  
Configuration Control 2  
Configuration Control 3  
Configuration Control 7  
SMM Address 0  
00h  
00h  
00h  
00h  
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