Instruction Set (Continued)
Table 9-27. Processor Core Instruction Set Summary (Continued)
Real
Mode
Prot’d Real Prot’d
Mode Mode Mode
Flags
O
F
D
F
I
F
T
F
S
F
Z
F
A
F
P
F
C
F
Clock Count
(Reg/Cache Hit)
Instruction
REP OUTS Output String
Opcode
Notes
h,m
F3 6[111w]
F3 A[101w]
-
-
-
-
-
-
-
-
-
24+4n 24+4n\
39+4n
b
b
REP STOS Store String
REPE CMPS Compare String
Find non-match
-
-
-
-
-
-
-
-
-
9+2n
9+2n
h
F3 A[011w]
F3 A[111w]
F2 A[011w]
F2 A[111w]
x
x
x
x
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
x
x
x
x
-
x
x
x
x
-
x
x
x
x
-
x
x
x
x
-
x
x
x
x
-
11+4n 11+4n
b
b
b
b
b
h
REPE SCAS Scan String
Find non-AL/AX/EAX
9+3n
9+3n
h
REPNE CMPS Compare String
Find match
11+4n 11+4n
h
h
REPNE SCAS Scan String
Find AL/AX/EAX
9+3n
9+3n
RET Return from Subroutine
Within Segment
C3
3
3
3
3
g,h,j,k,r
Within Segment Adding Immediate to SP
Intersegment
C2 ##
CB
10
10
13
13
Intersegment Adding Immediate to SP
CA ##
Protected Mode: Different Privilege Level
-Intersegment
-Intersegment Adding Immediate to SP
35
35
ROL Rotate Left
Register/Memory by 1
Register/Memory by CL
Register/Memory by Immediate
ROR Rotate Right
D[000w] [mod 000 r/m]
D[001w] [mod 000 r/m]
C[000w] [mod 000 r/m] #
x
u
u
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
x
x
x
2
2
2
2
2
2
b
b
h
h
Register/Memory by 1
Register/Memory by CL
Register/Memory by Immediate
D[000w] [mod 001 r/m]
D[001w] [mod 001 r/m]
C[000w] [mod 001 r/m] #
x
u
u
-
-
-
-
-
-
-
x
-
-
-
-
-
-
-
x
-
-
-
-
-
-
-
x
-
-
-
-
-
-
-
-
-
x
x
x
-
2
2
2
2
-
-
-
-
2
2
RSDC Restore Segment Register and Descriptor 0F 79 [mod sreg3 r/m]
-
-
-
-
11
11
11
57
1
11
11
11
57
1
s
s
s
s
s
s
s
s
RSLDT Restore LDTR and Descriptor
RSTS Restore TSR and Descriptor
RSM Resume from SMM Mode
SAHF Store AH in FLAGS
SAL Shift Left Arithmetic
0F 7B [mod 000 r/m]
0F 7D [mod 000 r/m]
0F AA
-
-
-
-
-
-
-
-
-
-
-
-
x
-
x
x
x
x
x
x
x
x
x
x
9E
Register/Memory by 1
D[000w] [mod 100 r/m]
D[001w] [mod 100 r/m]
C[000w] [mod 100 r/m] #
x
u
u
-
-
-
-
-
-
-
-
-
x
x
x
x
x
x
u
u
u
x
x
x
x
x
x
1
2
1
1
2
1
b
b
b
h
h
h
Register/Memory by CL
Register/Memory by Immediate
SAR Shift Right Arithmetic
Register/Memory by 1
D[000w] [mod 111 r/m]
D[001w] [mod 111 r/m]
C[000w] [mod 111 r/m] #
x
u
u
-
-
-
-
-
-
-
-
-
x
x
x
x
x
x
u
u
u
x
x
x
x
x
x
2
2
2
2
2
2
Register/Memory by CL
Register/Memory by Immediate
SBB Integer Subtract with Borrow
Register to Register
1[10dw] [11 reg r/m]
1[100w] [mod reg r/m]
1[101w] [mod reg r/m]
8[00sw] [mod 011 r/m] ###
1[110w] ###
x
-
-
-
x
x
x
x
x
1
1
1
1
1
2
1
1
1
1
1
2
Register to Memory
Memory to Register
Immediate to Register/Memory
Immediate to Accumulator (short form)
SCAS Scan String
A [111w]
x
-
-
-
-
-
-
-
-
-
-
-
-
-
x
-
x
-
x
-
x
-
x
-
b
h
h
h
h
SETB/SETNAE/SETC Set Byte on Below/Not Above or Equal/Carry
To Register/Memory 0F 92 [mod 000 r/m]
SETBE/SETNA Set Byte on Below or Equal/Not Above
1
1
1
1
1
1
To Register/Memory
0F 96 [mod 000 r/m]
-
-
-
-
-
-
SETE/SETZ Set Byte on Equal/Zero
To Register/Memory
0F 94 [mod 000 r/m]
-
-
-
-
-
-
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