Integrated Functions (Continued)
4.4 GRAPHICS PIPELINE
The graphics pipeline of the GXm processor includes a
BitBLT/vector engine which has been optimized for
Microsoft Windows. The hardware supports pattern gen-
eration, source expansion, pattern/source transparency,
and 256 ternary raster operations. The block diagram of
the graphics pipeline is shown in Figure 4-11.
4.4.1 BitBLT/Vector Engine
BLTs are initiated by writing to the GP_BLT_MODE regis-
ter, which specifies the type of source data (none, frame
buffer, or BLT buffer), the type of the destination data
(none, frame buffer, or BLT buffer), and a source expan-
sion flag.
Scratchpad RAM
and
BitBLT Buffers
C-Bus
Graphics
Pipeline
Output Aligner
Output Aligner
Pattern
Source
Hardware
Expansion
Internal Bus
Control Logic
Interface Unit
BE
PAT
BE
SRC
DST
Raster Operation
Register Access
DRAM Interface
X-Bus
Key:
BE = Byte Enable
PAT = Pattern Data
SRC = Source Data
DST = Destination Data
Memory
Controller
Figure 4-11. Graphics Pipeline Block Diagram
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