Integrated Functions (Continued)
4.3.7 SDRAM Interface Clocking
The delay for SDCLKIN must be designed so that it lags
the SDCLKs at the DRAM by approximately 2ns. The
delay should also include the SDCLK transmission line
delay. The SDCLK traces on the board need to be laid out
so there is no skew between each of the four sinks. These
guidelines allow the memory interface to be closer to the
DRAM specifications. They improve performance by run-
ning the SDCLK up to frequencies of 100 MHz and a CAS
latency of two.
The GXm processor drives the SDCLK to the SDRAMs;
one for each DIMM bank. All the control, data, and
address signals driven by the memory controller are sam-
pled by the SDRAM at the rising edge of SDCLK. SDCLK-
OUT is a reference signal used to generate SDCLKIN.
Read data is sampled by the memory controller at the ris-
ing edge of SDCLKIN.
SDCLK0
DIMM
SDCLK[3:0]
0
SDCLK1
SDCLKOUT
SDCLK2
DIMM
Geode™ GXm
1
SDCLK3
Delay
Processor
SDCLKIN
Figure 4-9. SDCLKIN Clocking
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