Integrated Functions (Continued)
The SDRAM interface timings are programmable. The
SHFTSDCLK bits in the MC_MEM_CNTRL2 register can
be used to change the relationship between SDCLK and
the control/address/data signals. To meet setup and hold
time requirements for SDRAM across different board lay-
outs, the SHFTSDCLK bits are used. SHFTSDCLK bit val-
ues are selected based upon the SDRAM signals loads
and the core frequency (refer to Table 7-10 on page 190 ).
ler runs off this processor clock. The memory clock is gen-
erated by dividing down the processor clock. SDCLK is
generated from the memory clock. In the example dia-
gram, the processor clock is running 6X times the PCI
clock and the memory clock is running in divide by 3
mode.
The SDRAM control, address, and data signals are driven
off edge "x" of the memory clock to be setup before edge
"y". With no shift applied, the control signals could end up
being latched on edge "x". A shift value of two or three
could be used so that SDCLK at the SDRAM is centered
around when the control signals change.
Figure 4-10 shows an example of how the SHFTSDCLK
bits setting affects SDCLK. The PCI clock is the input
clock to the GXm processor. The core clock is the internal
processor clock that is multiplied up. The memory control-
PCI Clock
Core Clock
(Internal)
0
1
2
x
3
4
5
y
6
Memory
Clock
(Internal)
CNTRL
Valid
SDCLK
(Note)
x
y
SDCLK
(Note)
4
3
2
1
0
Shift =
Note: The first SDCLK shows how SDCLK operates with the SHFTSDCLK bits = 000, no shift.
The second SDCLK shows how SDCLK operates with the SHFTSDCLK bits = 001, shift 0.5 core clock.
(See MC_MEMCNTRL2 bits [5:3], Table 4-16 on page 108 , for remaining decode values.)
Figure 4-10. Effects of SHFTSDCLK Programming Bits Example
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