Integrated Functions (Continued)
4.7.6 PCI Configuration Space Control Registers
this register all others will be forwarded as normal I/O
cycles to the PCI bus.
There
are
two
registers
in
this
category:
CONFIG_ADDRESS and CONFIG_DATA.
The CONFIG_DATA register contains the data that is sent
or received during a PCI configuration space access.
The CONFIG_ADDRESS register contains the address
information for the next configuration space access to
CONFIG_DATA. Only DWORD accesses are permitted to
Table 4-41 gives the bit formats for these two registers.
Table 4-41. PCI Configuration Registers
Bit
Name
Description
I/O Offset 0CF8h-0CFBh
CONFIG_ADDRESS Register (R/W)
Default Value = 00000000h
31
GFC_EN
CONFIG ENABLE: Determines when accesses should be translated to configuration cycles on the
PCI bus, or treated as a normal I/O operation. This register will be updated only on full DWORD I/O
operations to the CONFIG_ADDRESS. Any other accesses are treated as normal I/O cycles in
order to allow I/O devices to use BYTE or WORD registers at the same address and remain unaf-
fected. Once bit 31 is set high, subsequent accesses to CONFIG_DATA are then translated to con-
figuration cycles.
1 = Generate configuration cycles.
0 = Normal I/O cycles.
30:24
23:16
15:11
RSVD
BUS
Reserved: Set to 0.
Bus: Specifies a PCI bus number in the hierarchy of 1 to 256 buses.
DEVICE
Device: Selects a device on a specified bus. A device value of 00h will select the GXLV processor if
the bus number is also 00h. DEVICE values of 01h to 15h will be mapped to AD[31:11], so only 21 of
the 32 possible devices are supported. A DEVICE value of 00001b will map to AD[11] while a device
of 10101b will map to AD[31].
10:8
7:2
FUNCTION
REGISTER
TT
Function: Selects a function in a multi-function device.
Register: Chooses a configuration DWORD space register in the selected device.
1:0
Translation Type Bits: These bits indicate if the configuration access is local or one that requires
translation through other bridges to another PCI bus. When an access occurs to the CONFIG_DATA
address and the specified bus number matches the GXLV processor’s bus number (00h), then a
Type 0 translation takes place.
For a Type 0 translation, the CONFIG_ADDRESS register values are translated to AD lines on the
PCI bus. Note that bits [10:2] are passed unchanged. The DEVICE value is mapped to one of 21 AD
lines. The translation type bits are set to 00 to indicate a transaction on the local PCI bus.
When an access occurs to the CONFIG_DATA address and the specified bus number is not 00h
(Type 1), the GXLV processor passes this cycle to the PCI bus by copying the contents of the
CONFIG_ADDRESS register onto the AD lines during the address phase of the cycle while driving
the translation type bits AD[1:0] to 01.
I/O Offset 0CFCh-0CFFh
CONFIG_DATA (R/W)
Default Value = 00000000h
31:0
CONFIG_DATA
Configuration Data Register: Contains the data that is sent or received during a PCI configuration
space access. The register accessed is determined by the value in the CONFIG_ADDRESS regis-
ter. The CONFIG_DATA register supports BYTE, WORD, or DWORD accesses. To access this reg-
ister, bit 31 of the CONFIG_ADDRESS register must be set to 0 and a full DWORD I/O access must
be done. Configuration cycles are performed when bit 31 of the CONFIG_ADDRESS register is set
to 1
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