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30070-53 参数 Datasheet PDF下载

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型号: 30070-53
PDF下载: 下载PDF文件 查看货源
内容描述: 的Geode ™ GXLV处理器系列的低功耗X86集成解决方案 [Geode⑩ GXLV Processor Series Low Power Integrated x86 Solutions]
分类和应用: 外围集成电路时钟
文件页数/大小: 247 页 / 4117 K
品牌: NSC [ National Semiconductor ]
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Integrated Functions (Continued)  
4.7 PCI CONTROLLER  
The GXLV processor includes an integrated PCI controller  
with the following features.  
Configuration space is a physical address space unique to  
PCI. Configuration Mechanism #1 must be used by soft-  
ware to generate configuration cycles. Two DWORD I/O  
locations are used in this mechanism. The first DWORD  
location (CF8h) references a read/write register that is  
named CONFIG_ADDRESS. The second DWORD  
4.7.1 X-Bus PCI Slave  
16-byte PCI write buffer  
16-byte PCI read buffer from X-bus  
Supports cache line bursting  
Write/Inv line support  
Pacing of data for read or write operations with X-bus  
No active byte enable transfers supported  
address (CFCh) references  
CONFIG_DATA. The general method for accessing con-  
figuration space is to write value into  
a
register named  
a
CONFIG_ADDRESS that specifies a PCI bus, a device on  
that bus, and a configuration register in that device being  
accessed. A read or write to CONFIG_DATA will then  
cause the bridge to translate that CONFIG_ADDRESS  
value to the requested configuration cycle on the PCI bus.  
4.7.2 X-Bus PCI Master  
16 byte X-bus to PCI write buffer  
Configuration read/write Support  
Int Acknowledge support  
Lock conversion  
Support fast back-to-back cycles as slave  
4.7.5 Generating Special Cycles  
A special cycle is a broadcast message to the PCI bus.  
Two hardcoded special cycle messages are defined in the  
command encode: HALT and SHUTDOWN. Software can  
also generate special cycles by using special cycle gener-  
ation for configuration mechanism #1 as described in the  
PCI Specification 2.1 and briefly described here. To ini-  
tiate a special cycle from software, the host must write a  
value to CONFIG_ADDRESS encoded as shown in Table  
4-40.  
4.7.3 PCI Arbiter  
Fixed, rotating, hybrid, or ping-pong arbitration  
(programmable)  
Support four masters, three on PCI  
Internal REQ for CPU  
Master retry mask counter  
Master dead timer  
Resource or total system lock support  
The next value written to CONFIG_DATA is the encoded  
special cycle. Type 0 or Type 1 conversion will be based  
on the Bus Bridge number matching the GXLV proces-  
sors bus number of 00h.  
4.7.4 Generating Configuration Cycles  
Table 4-40. Special Cycle Code to CONFIG_ADDRESS  
31  
30  
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  
9
8
7
6
5
4
3
2
1
0
1
0 0 0 0 0 0 0  
RSVD  
Bus No. = Bridge  
BUS NUMBER  
1
1
1
1
1
1
1
1
0
0
0
0
0
0
CONFIG  
ENABLE  
DEVICE NUMBER FUNCTION REGISTER NUMBER TRANS  
NUMBER  
LATION  
TYPE  
Note: See Table 4-41 on page 167, bits [1:0] for translation type.  
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166  
Revision 1.1  
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