Integrated Functions (Continued)
Table 4-44. PCI Configuration Registers (Continued)
Bit
Name
Description
8
DPD
Data Parity Detected: This bit is set when all three conditions are met.
1) GXLV processor asserted PERR# or observed PERR# asserted;
2) GXLV processor is the master for the cycle in which the PERR# occurred; and
3) PE (bit 6 of Command Register) is enabled.
This bit can be cleared to 0 by writing a 1 to it.
7
FBS
Fast Back-to-Back Capable: As a target, the processor is capable of accepting Fast Back-to-Back
transactions.
This bit is always set to 1.
6:0
Index 08h
7:0
RSVD
Reserved: Set to 0.
Revision Identification Register (RO)
Default Value = 00h
RID (RO)
Revision ID (Read Only): This register contains the revision number of the GXLV design.
Index 09h-0Bh
Class Code Register (RO)
Default Value = 060000h
23:16
CLASS
Class Code: The class code register is used to identify the generic function of the device. The
GXLV processor is classified as a host bridge device (06).
15:0
Index 0Ch
7:0
RSVD (RO)
Reserved (Read Only)
Cache Line Size Register (RO)
Default Value = 00h
CACHELINE Cache Line Size (Read Only): The cache line size register specifies the system cache line size in units
of 32-bit words. This function is not supported in the GXLV processor.
Index 0Dh
Latency Timer Register (R/W)
Default Value = 00h
7:5
4:0
RSVD
Reserved: Set to 0.
LAT_TIMER Latency Timer: The latency timer as used in this implementation will prevent a system lockup resulting
from a slave that does not respond to the master. If the register value is set to 00h, the timer is disabled.
Otherwise, Timer represents the 5 MSBs of an 8-bit counter. The counter will reset on each valid data
transfer. If the counter expires before the next TRDY# is received active, then the slave is considered to
be incapable of responding, and the master will stop the transaction with a master abort and flag an
SERR# active. This would also keep the master from being retried forever by a slave device that contin-
ues to issue retries. In these cases, the master will also stop the cycle with a master abort.
Index 0Eh-3Fh
Index 40h
Reserved
Default Value = 00h
Default Value = 00h
PCI Control Function 1 Register (R/W)
7
6
RSVD
SW
Reserved: Set to 0.
Single Write Mode: GXLV as a PCI slave supports:
0 = Multiple PCI write cycles
1 = Single cycle write transfers on the PCI bus. The slave will perform a target disconnect with the first
data transferred.
5
4
SR
Single Read Mode: GXLV as a PCI slave supports:
0 = Multiple PCI read cycles.
1 = Single cycle read transfers on the PCI bus. The slave will perform a target disconnect with the first
data transferred.
RXBNE
Force Retry when X-Bus Buffers are Not Empty: GXLV as a PCI slave:
0 = Accepts the PCI cycle with data in the PCI master write buffers. The data in the PCI master write
buffers will not be affected or corrupted. The PCI master holds request active indicating the need to
access the PCI bus.
1 = Retries cycles if the PCI master X-Bus write buffers contain buffered data.
PCI Slave Write Buffer Enable: GXLV PCI slave write buffers: 0 = Disable; 1 = Enable.
PCI Cache Line Read Enable: Read operations from the PCI into the GXLV processor:
3
2
SWBE
CLRE
0 = Single cycle unless a read multiple or memory read line command is used.
1 = Cause a cache line read to occur.
1
0
XBE
X-Bus Burst Enable: Enable X-Bus bursting when an external master performs PCI write/invalidate
cycles. 0 = Disable; 1 = Enable.
(This bit does not control read bursting; bit 2 does.)
RSVD
Reserved: Should return a value of 0.
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