Integrated Functions (Continued)
4.6.4 Virtual VGA Register Descriptions
ters” on page 99 for instructions on accessing these regis-
ters.
This section describes the registers contained in the
graphics pipeline used for VGA emulation. The graphics
The registers are summarized in Table 4-38, followed by
detailed bit formats in Table 4-39.
pipeline
maps
200h
locations
starting
at
GX_BASE+8100h. Refer to Section 4.1.2 “Control Regis-
Table 4-38. Virtual VGA Register Summary
GX_BASE+
Memory Offset
Type
Name/Function
GP_VGA_WRITE
Default Value
8140h-8143h
8144h-8147h
8210h-8213h
8214h-8217h
R/W
xxxxxxxxh
Graphics Pipeline VGA Write Patch Control Register: Controls the VGA memory
write path in the graphics pipeline.
R/W
R/W
R/W
GP_VGA_READ
00000000h
xxxxxxxxh
xxxxxxxxh
Graphics Pipeline VGA Read Patch Control Register: Controls the VGA memory
read path in the graphics pipeline.
GP_VGA_BASE VGA
Graphics Pipeline VGA Memory Base Address Register: Specifies the offset of
the VGA memory, starting from the base of graphics memory.
GP_VGA_LATCH
Graphics Pipeline VGA Display Latch Register: Provides a memory mapped
way to read or write the VGA display latch.
www.national.com
164
Revision 1.1
NSC [ National Semiconductor ]
