Integrated Functions (Continued)
Table 4-44. PCI Configuration Registers
Bit
Name
Description
Index 00h-01h
Vendor Identification Register (RO)
Default Value = 1078h
31:0
VID (RO)
Vendor Identification Register (Read Only): The combination of this value and the device ID uniquely
identifies any PCI device. The Vendor ID is the ID given to National Semiconductor Corporation by the
PCI SIG.
Index 02h-03h
Device Identification Register (RO)
Default Value = 0001h
31:0
DIR (RO)
Device Identification Register (Read Only): This value along with the vendor ID uniquely identifies any
PCI device.
Index 04h-05h
PCI Command Register (R/W)
Default Value = 0007h
15:10
9
RSVD
FBE
Reserved: Set to 0.
Fast Back-to-Back Enable (RO): As a master, the GXLV processor does not support this function.
This bit returns 0.
8
7
SERR
WAT
SERR# Enable: This is used as an output enable gate for the SERR# driver.
Wait Cycle Control: GXLV processor does not do address/data stepping.
This bit is always set to 0.
6
PE
Parity Error Response:
0 = GXLV processor ignores parity errors on the PCI bus.
1 = GXLV processor checks for parity errors.
5
4
3
2
VPS
MS
VGA Palette Snoop: GXLV processor does not support this function.
This bit is always set to 0.
Memory Write and Invalidate Enable: As a master, the GXLV processor does not support this function.
This bit is always set to 0.
SPC
BM
Special Cycles: GXLV processor does not respond to special cycles on the PCI bus.
This bit is always set to 0.
Bus Master:
0 = GXLV processor does not perform master cycles on the PCI bus.
1 = GXLV processor can act as a bus master on the PCI bus.
1
0
MS
Memory Space: GXLV processor will always respond to memory cycles on the PCI bus.
This bit is always set to 1.
IOS
I/O Space: GXLV processor will not respond to I/O accesses from the PCI bus.
This bit is always set to 1.
Index 06h-07h
PCI Device Status Register (RO, R/W Clear)
Default Value = 0280h
15
DPE
Detected Parity Error: When a parity error is detected, this bit is set to 1.
This bit can be cleared to 0 by writing a 1 to it.
14
13
SSE
Signaled System Error: This bit is set whenever SERR# is driven active.
RMA
Received Master Abort: This bit is set whenever a master abort cycle occurs. A master abort will occur
whenever a PCI cycle is not claimed except for special cycles.
This bit can be cleared to 0 by writing a 1 to it.
12
11
RTA
STA
Received Target Abort: This bit is set whenever a target abort is received while the GXLV processor is
master of the cycle.
This bit can be cleared to 0 by writing a 1 to it.
Signaled Target Abort: This bit is set whenever the GXLV processor signals a target abort. A target
abort is signaled when an address parity occurs for an address that hits in the GXLV processor’s
address space.
This bit can be cleared to 0 by writing a 1 to it.
10:9
DT
Device Timing: The GXLV processor performs medium DEVSEL# active for addresses that hit into the
GXLV processor address space. These two bits are always set to 01.
00 = Fast
01 = Medium
10 = Slow
11 = Reserved
Revision 1.1
169
www.national.com
NSC [ National Semiconductor ]
