Integrated Functions (Continued)
The SDRAM interface timings are programmable. The
SHFTSDCLK bits in the MC_MEM_CNTRL2 register can
be used to change the relationship between SDCLK and
the control/address/data signals to meet setup and hold
time requirements for SDRAM across different board lay-
outs. SHFTSDCLK bit values are selected based upon the
SDRAM signals loads and the core frequency (refer to
Figures 6-9 and 6-10 on page 202).
ler runs off this core clock. The memory clock is gener-
ated by dividing down the core clock. SDCLK is generated
from the memory clock. In the example diagram, the pro-
cessor clock is running 6X times the PCI clock and the
memory clock is running in divide by 3 mode.
The SDRAM control, address, and data signals are driven
off edge “x1” of the memory clock to be setup before edge
“y1”. With no shift applied, the control signals could end up
being latched on edge “x2” of the SDCLK. A shift value of
two or three could be used so that SDCLK at the SDRAM
is centered around when the control signals change.
Figure 4-10 shows an example of how the SHFTSDCLK
bits setting affects SDCLK. The PCI clock is the input
clock to the GXLV processor. The core clock is the internal
processor clock that is multiplied up. The memory control-
PCI Clock
Core Clock
(Internal)
0
1
2
3
4
5
6
Memory
Clock
x1
y1
(Internal)
CNTRL
Valid
SDCLK
(Note)
x2
y2
SDCLK
(Note)
4
3
2
1
0
Shift =
Note: The first SDCLK shows how SDCLK operates with the SHFTSDCLK bits = 000, no shift.
The second SDCLK shows how SDCLK operates with the SHFTSDCLK bits = 001, shift 0.5 core clock.
(See MC_MEMCNTRL2 bits [5:3], Table 4-15 on page 114, for remaining decode values.)
Figure 4-10. Effects of SHFTSDCLK Programming Bits Example
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