Integrated Functions (Continued)
4.3.7 SDRAM Interface Clocking
The delay for SDCLKIN from SDCLKOUT must be
designed so that it lags the SDCLKs at the DRAM by
approximately 1 ns (check application notes for additional
information). The delay should also include the SDCLK
transmission line delay. All four SDCLK traces on the
board should be the same length, so there is no skew
between them. These guidelines allow the memory inter-
face to operate at a higher performance.
The GXLV processor drives the SDCLK to the SDRAMs;
one for each DIMM bank. All the control, data, and
address signals driven by the memory controller are sam-
pled by the SDRAM at the rising edge of SDCLK. SDCLK-
OUT is a reference signal used to generate SDCLKIN.
Read data is sampled by the memory controller at the ris-
ing edge of SDCLKIN.
SDCLK0
DIMM
SDCLK[3:0]
0
SDCLK1
SDCLKOUT
SDCLK2
DIMM
Geode™ GXLV
Processor
1
SDCLK3
Delay
SDCLKIN
Figure 4-9. SDCLKIN Clocking
Revision 1.1
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