Integrated Functions (Continued)
4.3.3 SDRAM Commands
MRS — The Mode Register command defines the specific
mode of operation of the SDRAM. This definition includes
the selection of burst length, burst type, and CAS latency.
CAS latency is the delay, in clock cycles, between the reg-
istration of a read command and the availability of the first
piece of output data.
This subsection discusses the SDRAM commands sup-
ported by the memory controller. Table 4-12 summarizes
these commands followed by detailed operational infor-
mation regarding each command. Refer to SDRAM device
specifications available from SDRAM manufacturer’s for
more detailed information.
The burst length is programmed by address bits MA[2:0],
the burst type by address bit MA3 and the CAS latency by
address bits MA[6:4].
Table 4-12. Basic Command Truth Table
The memory controller only supports a burst length of two
and burst type of interleave.
Name
Command
CS RAS CAS WE
MRS
PRE
ACT
Mode Register Set
Bank Precharge
L
L
L
L
L
L
L
H
H
L
L
The field value on MA[12:0] and BA[1:0] during the MRS
cycle are as shown in Table 4-13.
Bank activate/row-
address entry
H
PRE — The precharge command is used to deactivate
the open row in a particular component bank or the open
row in all (2 or 4, device dependent) component banks.
Address pin MA10 determines whether one or all compo-
nent banks are to be precharged. In the case where only
one component bank is to be precharged, BA[1:0] selects
which bank. Once a component bank has been pre-
charged, it is in the Idle state and must be activated prior
to any read or write commands.
WRT
Column address
entry/Write operation
L
L
H
H
X
L
L
L
X
L
L
H
X
H
READ
DESL
Column address
entry/Read operation
Control input inhibit/
No operation
H
L
RFSH* CBR Refresh or Auto
Refresh
Note: *This command is CBR (CAS-before-RAS) refresh
when CKE is high and self refresh when CKE is low.
Table 4-13. Address Line Programming during MRS Cycles
BA[1:0]
MA[12:7]
MA[6:4]
MA3
MA[2:0]
00
000000
CAS Latency:
1
001
000 = Reserved
010 = 2 CLK
100 = 4 CLK
110 = 6 CLK
001 = 1 CLK
011 = 3 CLK
101 = 5 CLK
111 = 7 CLK
Burst type is always
interleave.
Burst length is always 2.
128-bit transfer.
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