Integrated Functions (Continued)
Table 4-15. Memory Controller Registers
Bit
Name
Description
GX_BASE+ 8400h-8403h
MC_MEM_CNTRL1 (R/W)
Default Value = 248C0040h
31:29
28:26
25:23
MDHDCTL
MABAHDCTL
MEMHDCTL
MD High Drive Control: Controls the drive strength and slew rate of the memory data bus (MD[63:0])
during a write cycle:
000 = TRI-STATE
001 = Smallest drive strength
010 -110 = Represents gradual drive strength increase
111 = Highest drive strength
MA/BA High Drive Control: Controls the drive strength and slew rate of the memory address bus
including the memory bank address bus (MA[12:0] and BA[1:0]):
000 = TRI-STATE
001 = Smallest drive strength
010 -110 = Represents gradual drive strength increase
111 = Highest drive strength
Control High Drive/Slew Control: Controls the drive strength and slew rate of the memory control
signals (CASA#, CASB#, RASA#, RASB#, CKEA, CKEB, WEA#, WEA#, DQM[7:0], and CS[3:0]#):
000 = TRI-STATE
001 = Smallest drive strength
010 -110 = Represents gradual drive strength increase
111 = Highest drive strength
22
21
RSVD
RSVD
Reserved: Set to 0.
Reserved: Must be set to 0. Wait state on the X-Bus x_data during read cycles - for debug only.
SDRAM Clock Ratio: Selects SDRAM clock ratio:
20:18
SDCLKRATE
000 = Reserved
001 = ÷ 2
010 = ÷ 2.5
100 = ÷ 3.5
101 = ÷ 4
110 = ÷ 4.5
111 = ÷ 5
011 = ÷ 3 (Default)
Ratio does not take effect until the SDCLKSTRT bit (bit 17 of this register) transitions from 0 to 1.
17
SDCLKSTRT
Start SDCLK: Start operating SDCLK using the new ratio and shift value (selected in bits [20:18] of
this register): 0 = Clear; 1 = Enable.
This bit must transition from zero (written to zero) to one (written to one) in order to start SDCLK or to
change the shift value.
16:8
7:6
RFSHRATE
RFSHSTAG
Refresh Interval: This field determines the number of processor core clocks multiplied by 64 between
refresh cycles to the DRAM. By default, the refresh interval is 00h. Refresh is turned off by default.
Refresh Staggering: This field determines number of clocks between the RFSH commands to each
of the four banks during refresh cycles:
00 = 0 SDRAM clocks
01 = 1 SDRAM clocks (Default)
10 = 2 SDRAM clocks
11 = 4 SDRAM clocks
Staggering is used to help reduce power spikes during refresh by refreshing one bank at a time. If only
one bank is installed, this field must be set to 00.
5
2CLKADDR
Two Clock Address Setup: Assert memory address for one extra clock before CS# is asserted:
0 = Disable; 1 = Enable.
This can be used to compensate for address setup at high frequencies and/or high loads.
4
3
RFSHTST
XBUSARB
Test Refresh: This bit, when set high, generates a refresh request. This bit is only used for testing
purposes.
X-Bus Round Robin: When enabled, processor, graphics pipeline and non-critical display controller
requests are arbitrated at the same priority level. When disabled, processor requests are arbitrated at
a higher priority level. High priority display controller requests always have the highest arbitration prior-
ity: 0 = Enable; 1 = Disable.
2
SMM_MAP
SMM Region Mapping: Map the SMM memory region at GX_BASE+400000 to physical address
A0000 to BFFFF in SDRAM: 0 = Disable; 1 = Enable.
1
0
RSVD
Reserved: Set to 0.
SDRAMPRG
Program SDRAM: When this bit is set the memory controller will program the SDRAM MRS register
using LTMODE in MC_SYNC_TIM1.
This bit must transition from zero (written to zero) to one (written to one) in order to program the
SDRAM devices.
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