Integrated Functions (Continued)
4.3.1 Memory Array Configuration
have two or four component banks. Component bank
selection is done through the bank address (BA) lines.
The memory controller supports up to four 64-bit SDRAM
banks, with maximum of eight physical devices per bank.
Banks 0:1 and 2:3 must be identical configurations. Two
168-pin unbuffered SDRAM modules (DIMM) satisfy
these requirements Though the following discussion is
DIMM centric, DIMMs are not a system requirement. Each
DIMM receives a unique set of RAS, CAS, WE, and CKE
lines. Each DIMM can have one or two 64-bit DIMM
banks. Each DIMM bank is selected by a unique chip
select (CS). There are four chip select signals to choose
between a total of four DIMM banks. Each DIMM bank
also receives a unique SDCLK. Each DIMM bank can
For example, 16-Mbit SDRAM have two component banks
and 64-Mbit SDRAM have two or four component banks.
For single DIMM bank modules, the memory controller
can support two DIMMS with a maximum of eight compo-
nent banks. For dual DIMM bank modules, the memory
controller can support two DIMMs with a maximum of 16
component banks. Up to 16 banks can be open at the
same time. Refer to the SDRAM manufacturer’s specifica-
tion for more information on component banks.
DIMM 0
Bank 0
Bank 1
MA[12:0]
BA[1:0]
MD[63:0]
DQM[7:0]
RASA#
CASA#
WEA#
A[12:0]
BA[1:0]
MD[63:0]
DQM[7:0]
RAS#
A[12:0]
BA[1:0]
MD[63:0]
DQM[7:0]
RAS#
CAS#
WE#
CAS#
WE#
CS0#
S0#, S2#
CS1#
CKEA
S1#, S3#
CKE1
CKE0
SDCLK0
SDCLK1
CK0, CK2
CK1, CK3
Geode™ GXLV
Processor
DIMM 1
Bank 0
Bank 1
A[12:0]
BA[1:0]
MD[63:0]
DQM[7:0]
RAS#
A[12:0]
BA[1:0]
MD[63:0]
DQM[7:0]
RAS#
RASB#
CASB#
WEB#
CAS#
WE#
CAS#
WE#
CS2#
S0#, S2#
CS3#
CKEB
S1#, S3#
CKE1
CKE0
SDCLK2
SDCLK3
CK0, CK2
CK1, CK3
Figure 4-4. Memory Array Configuration
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