Integrated Functions (Continued)
4.3 MEMORY CONTROLLER
The memory controller arbitrates requests from the X-Bus
(processor and PCI), display controller, and graphics pipe-
line.
MHz and 100 MHz. The core clock can be divided down
from 2 to 5 in half clock increments to generate the
SDRAM clock. SDRAM frequencies between 79 MHz and
100 MHz are only supported for certain types of closed
systems and strict design rules must be adhered to. For
further details, contact your local National Semiconductor
technical support representative.
The GXLV processor supports LVTTL (low voltage TTL)
technology. LVTTL technology allows the SDRAM inter-
face of the memory controller to run at frequencies up to
100 MHz.
A basic block diagram of the memory controller is shown
in Figure 4-3.
The SDRAM clock is a function of the core clock. The
SDRAM bus can be run at speeds that range between 66
RFSH
Processor/PCI
Processor/PCI I/F
Control
DQM[7:0]
RASA#,RASB#
SDRAM
Sequence
Controller
CASA#,CASB#
CS[3:0]#
Display Controller
Timing
Controller
Display Controller I/F
Graphics Pipeline I/F
Arbiter
Control
WEA#/WEB#
CKEA, CKEB
Graphics Pipeline
Control
Configuration
Registers
Processor/PCI Address
MA[12:0]
BA[1:0]
Address
Control/MUX
Display Controller Address
Graphics Pipeline Address
Processor/PCI
Write Buffer (16 Bytes)
Processor/PCI Data
Display Controller Data
Graphics Pipeline Data
Display Controller
Write Buffer (16 Bytes)
MD[63:0]
Graphics Controller
Write Buffer (16 Bytes)
Read Buffer
(16 Bytes)
Clock Divider
2, 2.5, 3, 3.5, 4, 4.5, 5
Core Clock (ph2)
SDCLK[3:0]
Figure 4-3. Memory Controller Block Diagram
Revision 1.1
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