Integrated Functions (Continued)
Table 4-15. Memory Controller Registers (Continued)
Bit
Name
Description
GX_BASE+8404h-8407h
MC_MEM_CNTRL2 (R/W)
Default Value = 00000801h
31:14
13:11
RSVD
Reserved: Set to 0.
SDCLKHDCTL SDCLK High Drive/Slew Control: Controls the high drive and slew rate of SDCLK[3:0] and
SDCLK_OUT.
000 = Highest drive strength (no braking applied in the pads)
001 = Smallest drive strength
010 -110 = Represent gradual drive strength increase
111 = Highest drive strength
10
9
SDCLKOMSK# Enable SDCLK_OUT: Turn on the output. 0 = Enabled; 1 = Disabled.
SDCLK3MSK# Enable SDCLK3: Turn on the output. 0 = Enabled; 1 = Disabled.
SDCLK2MSK# Enable SDCLK2: Turn on the output. 0 = Enabled; 1 = Disabled.
SDCLK1MSK# Enable SDCLK1: Turn on the output. 0 = Enabled; 1 = Disabled.
SDCLK0MSK# Enable SDCLK0: Turn on the output. 0 = Enabled; 1 = Disabled.
8
7
6
5:3
SHFTSDCLK
Shift SDCLK: This function allows shifting SDCLK to meet SDRAM setup and hold time requirements.
The shift function will not take effect until the SDCLKSTRT bit (bit 17 of MC_MEM_CNTRL1) transi-
tions from 0 to 1:
000 = No shift
100 = Shift 2 core clocks
101 = Shift 2.5 core clocks
110 = Shift 3 core clocks
111 = Reserved
001 = Shift 0.5 core clock
010 = Shift 1 core clock
011 = Shift 1.5 core clock
Note: Refer to Figure 4-10 on page 124 for an example of SDCLK shifting.
Reserved: Set to 0.
2
1
RSVD
RD
Read Data Phase: Selects if read data is latched one or two core clock after the rising edge of
SDCLK: 0 = 1 core clock; 1 = 2 core clocks.
0
FSTRDMSK
Fast Read Mask: Do not allow core reads to bypass the request FIFO: 0 = Disable; 1 = Enable.
GX_BASE+8408h-840Bh
MC_BANK_CFG (R/W)
Default Value = 41104110h
31
30
RSVD
Reserved: Set to 0.
DIMM1_
DIMM1 Module Banks (Banks 2 and 3): Selects the number of module banks installed per DIMM for
MOD_BNK
DIMM1:
0 = 1 Module bank (Bank 2 only)
1 = 2 Module banks (Bank 2 and 3)
29
28
RSVD
Reserved: Set to 0.
DIMM1_
DIMM1 Component Banks (Banks 2 and 3): Selects the number of component banks per module
COMP_BNK
bank for DIMM1:
0 = 2 Component banks
1 = 4 Component banks
Banks 2 and 3 must have the same number of component banks.
Reserved: Set to 0.
27
RSVD
26:24
DIMM1_SZ
DIMM1 Size (Banks 2 and 3): Selects the size of DIMM1:
000 = 4 MB
001 = 8 MB
010 = 16 MB
011 = 32 MB
100 = 64 MB
101 = 128 MB
110 = 256 MB
111 = 512 MB (not supported)
This size is the total of both banks 2 and 3. Also, banks 2 and 3 must be the same size.
23
RSVD
Reserved: Set to 0.
22:20
DIMM1_PG_SZ DIMM1 Page Size (Banks 2 and 3): Selects the page size of DIMM1:
000 = 1 KB
001 = 2 KB
010 = 4 KB
011 = 8 KB
1xx = 16 KB
111 = DIMM1 not installed
Both banks 2 and 3 must have the same page size. When DIMM1 (neither bank 2 or 3) is not installed,
program all other DIMM1 fields to 0.
19:15
14
RSVD
Reserved: Set to 0.
DIMM0_
DIMM0 Module Banks (Banks 0 and 1): Selects number of module banks installed per DIMM for
MOD_BNK
DIMM0:
0 = 1 Module bank (Bank 0 only)
1 = 2 Module banks (Bank 0 and 1)
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