74LVC1G57-Q100
Nexperia
Low-power configurable multiple function gate
9
&&
9
&&
%
&
%
&
<
<
<
<
%
ꢁ
ꢄ
ꢂ
ꢀ
ꢅ
ꢃ
&
<
%
ꢁ
ꢄ
ꢂ
ꢀ
ꢅ
ꢃ
&
<
%
&
%
&
ꢀꢀꢁDDEꢂꢃꢂ
ꢀꢀꢁDDEꢂꢃꢇ
Fig 3. 2-input AND gate or 2-input NOR gate with
both inputs inverted
Fig 4. 2-input NAND gate with input B inverted or
2-input OR gate with inverted C input
9
&&
9
&&
$
&
<
<
$
&
ꢁ
ꢄ
ꢂ
ꢀ
ꢅ
ꢃ
&
<
<
<
ꢁ
ꢄ
ꢂ
ꢀ
ꢅ
ꢃ
&
<
$
&
$
$
&
$
ꢀꢀꢁDDEꢂꢃꢉ
ꢀꢀꢁDDEꢂꢃꢈ
Fig 5. 2-input NAND gate with input C inverted or
2-input OR gate with inverted A input
Fig 6. 2-input NOR gate or 2-input AND gate with
both inputs inverted
9
&&
9
&&
%
ꢁ
ꢄ
ꢂ
ꢀ
ꢅ
ꢃ
&
<
ꢁ
ꢄ
ꢂ
ꢀ
ꢅ
ꢃ
%
&
<
$
<
$
<
ꢀꢀꢁDDEꢂꢃꢃ
ꢀꢀꢁDDEꢂꢃꢆ
Fig 7. 2-input XNOR gate
Fig 8. Inverter
9
&&
%
ꢁ
ꢄ
ꢂ
ꢀ
ꢅ
ꢃ
%
<
<
ꢀꢀꢁDDEꢂꢆꢀ
Fig 9. Buffer
74LVC1G57_Q100
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Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 9 December 2016
4 of 16
NEXPERIA [ Nexperia ]
