µPD75304B,75306B,75308B
Table 8-1 Status of Each Hardware after Resetting (2/2)
RESET Input in Standby
Mode
RESET Input during
Operation
Hardware
Undefined
Counter (BT)
Undefined
Basic interval
timer
0
Mode register (BTM)
0
0
Counter (To)
0
FFH
Modulo register (TMOD0)
Mode Register (TM0)
Timer/event
counter
FFH
0
0
0,0
TOE0, TOUT F/F
0,0
0
Mode register (WM)
Watch timer
0
Held
Shift register (SIO)
Undefined
Serial interface
0
Operating mode register (CSIM)
SBI control register (SBIC)
Slave address register (SVA)
Processor clock control register (PCC)
System clock control register (SCC)
Clock output mode register (CLOM)
Display mode register (LCDM)
Display control register (LCDC)
Interrupt request flag (IRQ×××)
Interrupt enable flag (IE×××)
Interrupt master enable flag (IME)
INT0, 1, 2 mode registers (IM0, 1, 2)
Output buffer
0
0
0
Held
Undefined
0
0
Clock generator,
clock output
circuit
0
0
0
0
0
0
LCD controller
0
0
Reset (0)
Reset (0)
0
0
0
0
Interrupt function
0, 0, 0
OFF
Clear (0)
0
0, 0, 0
OFF
Clear (0)
0
Output latch
Digital port
I/O mode register (PMGA, B)
Pull-up resistor specification register
(POGA)
0
0
Bit sequential buffer (BSB0 to 3)
Undefined
Held
36
NEC [ NEC ]
