CHAPTER 3 CPU FUNCTIONS
3.2 CPU Register Set
The CPU registers of the V850ES/KF1, V850ES/KG1 and V850ES/KJ1 can be classified into two categories: a
general-purpose program register set and a dedicated system register set. All the registers have 32-bit width.
For details, refer to the V850ES Architecture User’s Manual.
(1) Program register set
(2) System register set
31
r0
0
31
EIPC
0
(Zero register)
(Interrupt status saving register)
r1
(Assembler-reserved register)
EIPSW (Interrupt status saving register)
r2
r3
(Stack pointer (SP))
(Global pointer (GP))
(Text pointer (TP))
FEPC
(NMI status saving register)
r4
FEPSW (NMI status saving register)
r5
r6
ECR
(Interrupt source register)
r7
r8
PSW
CTPC
(Program status word)
r9
r10
r11
r12
r13
r14
r15
r16
r17
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r28
r29
r30
r31
(CALLT execution status saving register)
CTPSW (CALLT execution status saving register)
DBPC
(Exception/debug trap status saving register)
DBPSW (Exception/debug trap status saving register)
CTBP
(CALLT base pointer)
(Element pointer (EP))
(Link pointer (LP))
31
PC
0
(Program counter)
User’s Manual U15862EJ3V0UD
99
NEC [ NEC ]
