CHAPTER 3 CPU FUNCTIONS
(2) NMI status saving registers (FEPC, FEPSW)
There are two NMI status saving registers, FEPC and FEPSW.
Upon occurrence of a non-maskable interrupt (NMI), the contents of the program counter (PC) are saved to
FEPC and the contents of the program status word (PSW) are saved to FEPSW.
The address of the next instruction following the instruction executed when a non-maskable interrupt occurs is
saved to FEPC, except for some instructions.
The current PSW contents are saved to FEPSW.
Since there is only one set of NMI status saving registers, the contents of these registers must be saved by the
program when multiple interrupt servicing is performed.
Bits 31 to 26 of FEPC and bits 31 to 8 of FEPSW are reserved (fixed to 0) for future function expansion.
31
2625
0
0
After reset
0xxxxxxxH
FEPC
0 0 0 0 0 0
(PC contents)
(x: Undefined)
31
8 7
After reset
000000xxH
FEPSW
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(PSW contents)
(x: Undefined)
(3) Interrupt source register (ECR)
Upon occurrence of an interrupt or an exception, the interrupt source register (ECR) holds the source of an
interrupt or an exception. The value held by ECR is the exception code coded for each interrupt source. This
register is a read-only register, and thus data cannot be written to it using the LDSR instruction.
31
1615
0
After reset
00000000H
ECR
FECC
EICC
Bit position
31 to 16
15 to 0
Bit name
Description
FECC
EICC
Non-maskable interrupt (NMI) exception code
Exception, maskable interrupt exception code
User’s Manual U15862EJ3V0UD
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NEC [ NEC ]
