CHAPTER 3 CPU FUNCTIONS
3.2.2 System register set
System registers control the status of the CPU and hold interrupt information.
Read from and write to system registers are performed by setting the system register numbers shown below with
the system register load/store instructions (LDSR, STSR instructions).
Table 3-2. System Register Numbers
Register No.
System Register Name
Operand Specification Enabled
LDSR
STSR
Instruction
Instruction
0
Interrupt status saving register (EIPC)Note 1
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
No
1
Interrupt status saving register (EIPSW)Note 1
NMI status saving register (FEPC)Note 1
NMI status saving register (FEPSW)Note 1
Interrupt source register (ECR)
2
3
4
5
Program status word (PSW)
Yes
No
6 to 15
Reserved numbers for future function expansion (The operation is not guaranteed
if accessed.)
16
17
CALLT execution status saving register (CTPC)
CALLT execution status saving register (CTPSW)
Exception/debug trap status saving register (DBPC)
Exception/debug trap status saving register (DBPSW)
CALLT base pointer (CTBP)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
18
YesNote 2
YesNote 2
Yes
19
20
21 to 31
Reserved numbers for future function expansion (The operation is not guaranteed
if accessed.)
No
Notes 1. Since only one set of these registers is available, the contents of this register must be saved by the
program when multiple interrupt servicing is enabled.
2. Can be accessed only during DBTRAP instruction execution.
Caution Even if bit 0 of EIPC, FEPC, or CTPC is set to (1) by the LDSR instruction, bit 0 is ignored during
return with the RETI instruction following interrupt servicing (because bit 0 of PC is fixed to 0). If
setting a value to EIPC, FEPC, and CTPC, set an even number (bit 0 = 0).
User’s Manual U15862EJ3V0UD
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NEC [ NEC ]
